category: System-Level Design

category: Auto, Security & Edge AI

Have It All With No-Compromise DFT
By Geir Eide - 28 Jan, 2021 - Comments: 0

The dramatic rise in manufacturing test time for today’s large and complex SoCs is rooted in the use of traditional approaches to moving scan test data from chip-level pins to core-level scan channels. The pin-multiplexing (mux) approach works fine for smaller designs but can become problematic with an increase in the number of cores and the design complexity on today’s SoCs. The next revol... » read more

AI And ML Applications Require Advanced Datapath Verification
By Kiran Vittal - 28 Jan, 2021 - Comments: 0

In popular usage, the term “artificial intelligence” (AI) once conjured up images of robot armies subjugating humans or evil computers outsmarting their users, as in '2001: A Space Odyssey.' In recent years, AI has become a part of daily life for much of the planet’s population. People use voice commands to interact with their smartphones, smart speakers and even TV remote controls. Sophi... » read more

Roaring ’20s For The Chip Industry
By Brian Bailey - 28 Jan, 2021 - Comments: 0

2020 was a good year for the semiconductor industry and the EDA industry that fuels it, but 2021 has the opportunity to be even better. New end application markets continue to open, and what were once seen as technical hurdles are leading to a multitude of innovative solutions, all of which need suitable tooling. No company can afford to invest everywhere, and so for EDA companies, their rel... » read more

Bug Escapes And The Definition Of Done
By Hagai Arbel - 28 Jan, 2021 - Comments: 0

National Semiconductor's design center (NSTA) in Herzliya was the place where I fell in love with chip verification. I joined the team in 1999, still during my BSc, and met a group of innovators with a passion to create great ASICs and improve the way we did it at all costs. It was fast-moving learning for me, both on the verification engineering and verification management sides of things. ... » read more

Big Changes In Verification
By Ann Mutschler - 28 Jan, 2021 - Comments: 0

Verification is undergoing fundamental change as chips become increasingly complex, heterogeneous, and integrated into larger systems. Tools, methodologies, and the mindset of verification engineers themselves are all shifting to adapt to these new designs, although with so many moving pieces this isn't always so easy to comprehend. Ferreting out bugs in a design now requires a multi-faceted... » read more

Hyperscaling The 21st Century Engineer
By Frank Schirrmeister - 28 Jan, 2021 - Comments: 0

While January is the month of predictions for many, I have made it a habit to look back and see how previous forward-looking assessments have worked out. It is fascinating to see how many past predictions were off and how little has changed in some areas. Twenty years ago, in January 2001, the front cover of IEEE Spectrum set the theme of ubiquitous connectivity in an always-on world. Some o... » read more

Taming Non-Predictable Systems
By Brian Bailey - 28 Jan, 2021 - Comments: 0

How predictable are semiconductor systems? The industry aims to create predictable systems and yet when a carrot is dangled, offering the possibility of faster, cheaper, or some other gain, decision makers invariably decide that some degree of uncertainty is warranted. Understanding uncertainty is at least the first step to making informed decisions, but new tooling is required to assess the im... » read more

ISA Ownership Matters: A Tale of Three ISAs
By Roddy Urquhart - 28 Jan, 2021 - Comments: 0

An instruction set architecture (ISA) is crucial to the development of processors and their software ecosystems. In the last half century, the majority of ISAs have been owned by single companies, whether product companies for their own chips/systems or processor IP companies who licensed their processors to chip developers. Does ISA ownership matter? Let’s consider three proprietary ISAs a... » read more

Streaming Scan Network
By Siemens EDA - 27 Jan, 2021 - Comments: 0

The increasing complexity in large System on Chip (SoC) designs present challenges to design-for-test (DFT). Hierarchical DFT alleviates some of those challenges, by itself, is no longer enough. Adding Tessent Streaming Scan Network (SSN) technology eliminates the difficult and costly trade-offs between test implementation effort and manufacturing test cost by decoupling core-level and chip-lev... » read more

Blog Review: Jan. 27
By Jesse Allen - 27 Jan, 2021 - Comments: 0

Synopsys' Godwin Maben finds that applications like high-performance computing and AI are bringing new dynamics to the power equation, and the key power considerations for chip design that will likely emerge over the course of the year. Siemens EDA's Harry Foster checks out trends in verification technology adoption for IC and ASIC design, with increasing numbers of designs using both dynami... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy