category: System-Level Design

category: Auto, Security & Edge AI

Verification Convergence: Problem Definition
By Hagai Arbel - 30 Nov, 2020 - Comments: 0

A while ago, I had to go to the ER with my friend who suddenly had a numb feeling in his face. He felt okay (and everything else is okay with him), but better be safe than sorry. While the doctor examined him I noticed that before tracing the problem itself, she asked some questions to rule-out a problem she was already familiar with and that can manifest itself in similar ways. Only then, a... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 Nov, 2020 - Comments: 0

AI Mythic debuted its Analog Matrix Processor for edge AI applications such as smart home, AR/VR, drones, video surveillance, smart city, and industrial. The M1108 AMP combines 108 tiles made up of an array of flash cells and ADCs, a 32-bit RISC-V nano-processor, a SIMD vector engine, SRAM, and a high-throughput Network-on-Chip router. It uses 40nm technology and the company says typical power... » read more

Blog Review: Nov. 25
By Jesse Allen - 25 Nov, 2020 - Comments: 0

Mentor's Harry Foster finds growing complexity in FPGA design by looking at the number of embedded microprocessors, asynchronous clock domains, and safety/security features in the 2020 Wilson Research Group Functional Verification Study. Cadence's Paul McLellan points to the interim SRC/SIA Decadal Plan for Semiconductors and five big shifts it identifies in information and communication tec... » read more

What Interested You In 2020
By Brian Bailey - 24 Nov, 2020 - Comments: 0

In business you are always told to follow the money, but for us it is more important to follow the readership. If we are not writing what you want to read, then we are missing the mark. I like to review the ones that have garnered the most attention, in part to see if that will influence what I write about for 2021, but also to find out where the industry is looking for the most help. As Sem... » read more

Silo Busting In The Design Flow
By Brian Bailey - 24 Nov, 2020 - Comments: 0

An increasing number of dependencies in system design are forcing companies, people, tools, and flows to become more collaborative. Design and EDA companies must adapt to this new reality because it has become impossible for anyone to do it all by themselves. Moreover, what happens in manufacturing and packaging needs to be considered up front, and what gets designed in the design phase may ... » read more

System Design For Next-Generation Hyperscale Data Centers
By Frank Schirrmeister - 24 Nov, 2020 - Comments: 0

As we are in the process of hyperscaling the large volumes of data that our devices and sensors create, processing this data along the way at far and near edges, and transmitting the hard-to-imagine volumes of data through networks to data centers for processing, the data center itself is undergoing a fundamental shift with new networking and architecture co-design opportunities. In a previous ... » read more

Impact Of Instruction Memory On Processor PPA
By Roddy Urquhart - 24 Nov, 2020 - Comments: 0

The area of any part of a design contributes both to the silicon cost and to the power consumption. A simplistic following of the “A” in a processor IP vendor’s PPA numbers can be misleading. A processor is never in isolation but is part of a subsystem additionally including instruction memory, data memory, and peripherals. In most cases, instruction memory will be dominant and the proc... » read more

Using AI And Bugs To Find Other Bugs
By Ann Mutschler - 24 Nov, 2020 - Comments: 0

Debug is starting to be rethought and retooled as chips become more complex and more tightly integrated into packages or other systems, particularly in safety- and mission-critical applications where life expectancy is significantly longer. Today, the predominant bug-finding approaches use the ubiquitous constrained random/coverage driven verification technology, or formal verification techn... » read more

Brute-Force Analysis Not Keeping Up With IC Complexity
By Brian Bailey - 24 Nov, 2020 - Comments: 0

Much of the current design and verification flow was built on brute force analysis, a simple and direct approach. But that approach rarely scales, and as designs become larger and the number of interdependencies increases, ensuring the design always operates within spec is becoming a monumental task. Unless design teams want to keep adding increasing amounts of margin, they have to locate th... » read more

ESD P2P And CD Verification Doesn’t Have To Be Hard
By Abdellah Bakhali - 24 Nov, 2020 - Comments: 0

As a designer or verification engineer, you’re fighting the effects of electrostatic discharge (ESD) in your integrated circuit (IC) designs all the time. ESD is one of those frustrating issues that can challenge even the most experienced designers. Once an IC is in the market, unexpected electrical shorts will cause immediate failure or dielectric breakdown will result in gradual circuit deg... » read more

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