category: System-Level Design

category: Auto, Security & Edge AI

System Bits: Dec. 18
By Jeff Dorsch - 18 Dec, 2018 - Comments: 0

AI studies at Stanford Language processing is a leading area in artificial intelligence research, Stanford University reports. “We’re trying to inform the conversation about artificial intelligence with hard data,” says Yoav Shoham, professor of computer science, emeritus, adding, “Language is the ultimate frontier of AI research because you can express any thought or idea in langua... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Dec, 2018 - Comments: 0

The MIPI Alliance released MIPI I3C Basic v1.0, a subset of the MIPI I3C sensor interface specification that bundles 20 of the most commonly needed I3C features for developers and other standards organizations. The royalty-free specification includes backward compatibility with I2C, 12.5 MHz multi-drop bus that is over 12 times faster than I2C supports, in-band interrupts to allow slaves to not... » read more

Blog Review: Dec. 12
By Jesse Allen - 12 Dec, 2018 - Comments: 0

Mentor's Harry Foster checks out how much time and effort is spent on verification of FPGAs and points to the increasing demand for verification engineers. Cadence's Paul McLellan digs into IC Insights' year-end report to see how some of the top semiconductor companies stack up. Synopsys' Taylor Armerding warns that air gaps, a valuable barrier against cyberattacks, are disappearing from ... » read more

System Bits: Dec. 11
By Jeff Dorsch - 11 Dec, 2018 - Comments: 0

Calculating the costs of autonomous vehicles The development of autonomous vehicle technology commands a lot of media coverage. Little reporting has been devoted to the costs of operating AVs, a subject that developers don’t discuss in general. The Houston-Galveston Area Council’s website recently divulged contract figures with two startups, Drive.ai and EasyMile. For Silicon Valley-bas... » read more

Week In Review: Design, Low Power
By Jesse Allen - 07 Dec, 2018 - Comments: 0

RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

Mitigating Risk Through Verification
By Ann Mutschler - 05 Dec, 2018 - Comments: 0

Verification is all about mitigating risk, and one of the growing issues alongside of increasing complexity and new architectures is coverage. The whole notion of coverage is making sure a chip will work as designed. That requires determining the effectiveness of the simulation tests that stimulate it, and its effectiveness in terms of activating structures of functional behavior and design.... » read more

Blog Review: Dec. 5
By Jesse Allen - 05 Dec, 2018 - Comments: 0

Mentor's Harry Foster digs into verification effectiveness in FPGA projects and what it means that so many non-trivial bugs escape into production. Cadence's Paul McLellan checks out an effort to integrate photonics with CMOS and find the tradeoffs in three different approaches, plus the view of photonics as applied to military aircraft. Synopsys' Richard Solomon shares some highlights on... » read more

Formal Signoff
By Ed Sperling - 04 Dec, 2018 - Comments: 0

Xiaolin Chen, senior AE at Synopsys, looks at what’s good enough coverage, what makes one assertion better than another, and where the potential holes are in verification. https://youtu.be/nBtKE0gDHBU » read more

System Bits: Dec. 4
By Ann Mutschler - 04 Dec, 2018 - Comments: 0

High precision system for self-driving car navigation Based on technology developed by ETH Zurich researchers, Fixposition is a spin-off specializing in real-time navigation systems for use in self-driving vehicles, robots or industrial drones, which uses a combination of satellite-based positioning systems such as GPS with computer vision technologies to achieve an unparalleled degree of prec... » read more

Week In Review: Design, Low Power
By Jesse Allen - 30 Nov, 2018 - Comments: 0

Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

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