Blog Review: Oct. 31


Mentor's Joe Hupcey III digs into handling memories effectively with formal through abstraction and the easiest ways to address memory-related inconclusive results. Cadence's Paul McLellan explains DARPA's CHIPS program that aims to lower semiconductor design costs through chiplet-based designs, the current status of the work, and what the next steps will be. Synopsys' Sangeeta Kulkarni c... » read more

The Impact of Domain Crossing on Safety


Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

System Bits: Oct. 30


Ethics, regional differences for programming autonomous vehicles MIT researchers have revealed some distinct global preferences concerning the ethics of autonomous vehicles, as well as some regional variations in those preferences based on a recently completed survey. [caption id="attachment_24139620" align="alignleft" width="300"] Ethical questions involving autonomous vehicles are the foc... » read more

The Impact of Moore’s Law Ending


Over the past couple of process nodes the chip industry has come to grips with the fact that Moore's Law is slowing down or ending for many market segments. What isn't clear is what comes next, because even if chipmakers stay at older nodes they will face a series of new challenges that will drive up costs and increase design complexity. Chip design has faced a number of hurdles just to get ... » read more

Week In Review: Design, Low Power


Tools OneSpin launched a formal verification tool that integrates with all major simulators, coverage databases and viewers, and chip design verification planning tools to provide a comprehensive view of verification progress. Comprised of two new formal apps, it can identify unreachable coverage points and provide them to the simulator to reduce wasted effort. Synopsys released the latest ... » read more

The Race To Design Larger Systems


For more than a decade, tools vendors and design houses have been talking about leveraging their tools and expertise to help design systems of systems. They're finally getting their chance. The basic idea behind this strategy has always been that issues inside any electronic system—performance, power, signal integrity, area—have all been dealt all the way down to the sub-atomic level in ... » read more

Reduction In First Silicon Success


Every two years, Harry Foster, chief scientist for Mentor, a Siemens Business, works with Wilson Research to do a verification study. Those studies have influenced many in the industry, indicating where users are experiencing the most pain, spending their time, growing their team sizes and where money would be best spent. However, over the past four years, the ASIC industry has basically been i... » read more

Make-Or-Break Time For Portable Stimulus


I’m pretty upbeat when it comes to portable stimulus. Or maybe it’d be better to say I’m pretty upbeat on the idea of portable stimulus. While doing my best to brush aside the usual EDA propaganda (propaganda I’ve found to be a bit haphazard, but more on that in a minute), I’ve put a lot of thought into how portable stimulus could fit into verification flows, the purpose of using it a... » read more

Integrating Results And Coverage From Simulation And Formal


Not so long ago, formal verification was considered an exotic technology used only by specialists for specific verification challenges such as cache coherency. As chips have grown ceaselessly in size and complexity, the traditional verification method of simulation could not keep pace. The task of generating and running enough tests consumed enormous resources in terms of engineers, simulation ... » read more

What Makes A Good AI Accelerator


The rapid growth and dynamic nature of AI and machine learning algorithms is sparking a rush to develop accelerators that can be optimized for different types of data. Where one general-purpose processor was considered sufficient in the past, there are now dozens vying for a slice of the market. As with any optimized system, architecting an accelerator — which is now the main processing en... » read more

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