category: System-Level Design

category: Auto, Security & Edge AI

Blog Review: Nov. 21
By Jesse Allen - 21 Nov, 2018 - Comments: 0

Cadence's Paul McLellan looks at why specialized architectures will be the future of processor development, why general purpose processors are a poor match for AI, and other highlights from the recent Linley Processor Conference. Mentor's Harry Foster focuses on what's happening in FPGA design and the factors that are adding to increasing design and verification complexity. Synopsys' Lewi... » read more

Week In Review: Design, Low Power
By Jesse Allen - 21 Nov, 2018 - Comments: 0

Cadence taped out a complete GDDR6 memory IP solution consisting of PHY, controller and Verification IP on Samsung's 7LPP process. The GDDR6 IP allows up to 16Gb/sec bandwidth per pin, or over 500Gb/sec peak bandwidth between the SoC and each GDDR6 memory die. It is targeted at very high-bandwidth applications including AI, cryptocurrency mining, graphics, ADAS and HPC. ClioSoft debuted a So... » read more

System Bits: Nov. 20
By Ann Mutschler - 20 Nov, 2018 - Comments: 0

Designing transistors that don’t overheat In order to avoid heat-induced voids and cracking that can cause chips and circuits to fail, Stanford University and University of California at Davis researchers have developed a way to not only manage heat, but help route it away from delicate devices that leverages a thermal transistor, which is a nanoscale switch that can conduct heat away from ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Nov, 2018 - Comments: 0

Tools & Standards Mentor uncorked a PCB design platform for non-specialist PCB engineers focused on multi-dimensional verification. The Xpedition platform can integrate a range of verification tools within a singular authoring environment, providing automatic model creation, concurrent simulation, cross probing from results, and error reviews to identify problems at the schematic or layout... » read more

Blog Review: Nov. 14
By Jesse Allen - 14 Nov, 2018 - Comments: 0

Mentor's Jin Hou and Joe Hupcey III explain two fundamental characteristics of formal analysis that simplify things for the formal algorithm and provide better wall clock run time and memory usage performance. Cadence's Paul McLellan shares highlights from five presentations all discussing what's behind AI's movement to edge devices, the vast amount of investment going into the area, and whe... » read more

System Bits: Nov. 13
By Ann Mutschler - 13 Nov, 2018 - Comments: 0

Deep learning device identifies airborne allergens To identify and measure airborne biological particles, or bioaerosols, that originate from living organisms such as plants or fungi, UCLA researchers have invented a portable device that uses holograms and machine learning. The device is trained to recognize five common allergens — pollen from Bermuda grass, oak, ragweed and spores from t... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Nov, 2018 - Comments: 0

M&A SMIT Holdings acquired S2C, a provider of FPGA prototyping hardware and software as well as interfaces and accessories, for $19 million, plus up to US$2 million in milestone based payments to the key management team. S2C was founded in 2003. SMIT, based in Hong Kong, makes pay TV broadcasting access and mobile point-of-sale payment systems for the Chinese market. Tools & IP Syn... » read more

Blog Review: Nov. 7
By Jesse Allen - 07 Nov, 2018 - Comments: 0

Arm's Shidhartha Das looks into maximizing the benefits of power delivery networks and explains a non-intrusive technique using an on-chip digital storage oscilloscope that can directly sample the power-rails to probe potential runtime bugs due to power delivery weaknesses. Synopsys' Snigdha Dua argues that scrambling is one of the most important features introduced in HDMI 2.0 and takes a l... » read more

System Bits: Nov. 6
By Ann Mutschler - 06 Nov, 2018 - Comments: 0

Keeping data private To preserve privacy during data collection from the Internet, Stanford University researchers have developed a new technique that maintains personal privacy given that the many devices part of our daily lives collect information about how we use them. Stanford computer scientists Dan Boneh and Henry Corrigan-Gibbs created the Prio method for keeping collected data priva... » read more

The Week In Review: Design
By Jesse Allen - 02 Nov, 2018 - Comments: 0

M&A GlobalFoundries formed Avera Semiconductor, a wholly-owned subsidiary focused on custom ASIC designs. While Avera will use its relationship with GF for 14/12nm and more mature technologies, it has a foundry partnership lined up for 7nm. The new company's IP portfolio includes high-speed SerDes, high-performance embedded TCAMs, ARM cores and performance and density-optimized embedded SR... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy