category: System-Level Design

category: Auto, Security & Edge AI

Implementing Mathematical Algorithms In Hardware For Artificial Intelligence
By John Swanson - 25 Oct, 2018 - Comments: 0

Petabytes of data efficiently travels between edge devices and data centers for processing and computing of AI functions. Accurate and optimized hardware implementations of functions offload many operations that the processing unit would have to execute. As the mathematical algorithms used in AI-based systems evolve, and in some cases stabilize, the demand to implement them in hardware increase... » read more

Improving Library Characterization Quality And Runtime With Machine Learning
By Megan Marsh - 25 Oct, 2018 - Comments: 0

By Megan Marsh and Wei-Lii Tan Today’s semiconductor applications, ranging from advanced sensory applications, IoT, edge computing devices, high performance computing, to dedicated A.I. chips, are constantly pushing the boundaries of attainable power, performance, and area (PPA) metrics. The race to design and ship these innovative devices has resulted in a focused, time-to-market-driven e... » read more

EDA Cloud Adoption Hits Speed Bumps
By Brian Bailey - 25 Oct, 2018 - Comments: 0

If moving semiconductor design to the Cloud was easy and beneficial, everyone would be doing it. But so far, few have done more than dip a toe. The level of difficulty associated with migrating to the Cloud varies, depending upon who you talk to. The reality is that not everyone makes it as easy as it could be, or is not willing to put the necessary effort into making it easier. There is cer... » read more

High-Speed Serial Comms: Getting There Is Half The Fun
By Mike Gianfagna - 25 Oct, 2018 - Comments: 0

Last month I wrote about our 56G SerDes announcement – silicon validated and running in Rome at a major show. We had a great time at that show and got a lot of compliments about the quality and flexibility of our SerDes. These kinds of unfiltered, unsolicited customer comments are really what makes it all worthwhile. It was a gratifying and exciting time. This month, we’re at it again. O... » read more

Building AI SoCs
By Ed Sperling - 25 Oct, 2018 - Comments: 0

Ron Lowman, strategic marketing manager at Synopsys, looks at where AI is being used and how to develop chips when the algorithms are in a state of almost constant change. That includes what moves to the edge versus the data center, how algorithms are being compressed, and what techniques are being used to speed up these chips and reduce power. https://youtu.be/d32jtdFwpcE    ... » read more

The Power Of Ecosystems At Arm TechCon 2018
By Frank Schirrmeister - 25 Oct, 2018 - Comments: 0

I have long been fascinated by the workings of ecosystems. Last week’s Arm TechCon in San Jose was a textbook example of how ecosystems work, overlap and how the electronics development work is indeed like a village—it takes many players to make things happen to enable end users to receive the latest gadgets like phones, fitness trackers, electronic watches, etc. The game of electronic ecos... » read more

From Physics To Applications
By Ed Sperling - 25 Oct, 2018 - Comments: 0

Jack Harding, president and CEO of eSilicon, sat down with Semiconductor Engineering to talk about the shift toward AI and advanced packaging, and the growing opportunities at 7nm at a time when Moore's Law has begun slowing down. What follows are excerpts of that conversation. SE: Over the past year, the industry has changed its focus from shrinking features and consolidation to all sorts o... » read more

A Method to Measure Die Pad Capacitance
By Cadence - 24 Oct, 2018 - Comments: 0

This paper defines a method to measure the chip die pad capacitance using time delay reflectometry (TDR). This method is useful for measuring the low-value capacitance that is present at the end of a transmission line. In all protocol specifications, pad capacitance is an important electrical parameter to be measured because it directly affects the bandwidth. However, it is a challenge to me... » read more

System-Level, Post-Layout Electrical Analysis For High-Density Advanced Packaging
By Mentor, a Siemens Business - 24 Oct, 2018 - Comments: 0

As HDAP designs become more popular, the need for post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification (DRC and LVS) is growing. Mentor provides an accurate, automated flow that generates the required HDAP netlist for simulation/STA to enable HDAP designers to ensure that the HDAP will perform as designed. To read more, click here. » read more

Blog Review: Oct. 24
By Jesse Allen - 24 Oct, 2018 - Comments: 0

Arm's Shidhartha Das digs into Power Delivery Networks with a look at how the specific roles of different components work to provide smooth supply conditions. In a video, VLSI Research's Dan Hutcheson chats with D2S CEO Aki Fujimura about the state of the photomask market, EUV optimism, and the most interesting findings from this year's eBeam Initiative survey. Synopsys' Prasad Subudhi K.... » read more

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