category: System-Level Design

category: Auto, Security & Edge AI

So Many Waivers Hiding Issues
By Brian Bailey - 05 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Week In Review: Design, Low Power
By Jesse Allen - 05 Oct, 2018 - Comments: 0

Mirabilis Design debuted an AI-driven tool for performance analysis and architecture exploration of SoCs and embedded systems. VisualSim AI Processor Generator creates pipeline-accurate models that have port integration with standard buses and memories, which is used to compare different processor families, optimize the specification and identify system bottlenecks. The generated model supports... » read more

Performance Benchmarking Embedded FPGAs
By Flex Logix - 03 Oct, 2018 - Comments: 0

When evaluating the performance of an embedded FPGA, one needs to evaluate the performance of each of the individual modules that make up an FPGA. The basic modules are: Reconfigurable logic building blocks (RBB-Logic), Fine-granularity logic containing LUTs, carry-forwarding adder chain, and flip-flops Reconfigurable DSP building blocks (RBB-DSP), Medium-granularity arith... » read more

Cloud Drives Changes In Network Chip Architectures
By Ann Mutschler - 03 Oct, 2018 - Comments: 0

Cloud data centers have changed the networking topology and how data moves throughout a large data center, prompting significant changes in the architecture of the chips used to route that data and raising a whole new set of design challenges. Cloud computing has emerged as the fast growing segment of the data center market. In fact, it is expected to grow three-fold in the next few years, a... » read more

Blog Review: Oct. 3
By Jesse Allen - 03 Oct, 2018 - Comments: 0

Applied's Buvna Ayyagari-Sangamalli notes that the requirements of AI are challenging the entire design ecosystem, and while new materials are necessary, so is keeping up the current pace of architecture and EDA development. Mentor's Joe Hupcey III digs into how to handle counters effectively with formal by reducing their size or replacing them with abstract models to allow formal engines to... » read more

System Bits: Oct. 2
By Ann Mutschler - 02 Oct, 2018 - Comments: 0

Computer algorithms exhibit prejudice based on datasets Researchers at Cardiff University and MIT have shown that groups of autonomous machines are capable of demonstrating prejudice by identifying, copying, and learning this behavior from one another. The team noted that while it may seem that prejudice is a human-specific phenomenon that requires human cognition to form an opinion of, or ... » read more

Using High-Bandwidth Memory
By Ed Sperling - 01 Oct, 2018 - Comments: 0

eSilicon’s Tim Horel talks about HBM, what engineers need to know to work with this technology, and how it integrates with ASICs at advanced nodes. https://youtu.be/0Yq2XHGF6UE » read more

EDA, IP Revenues Up Again
By Ed Sperling - 01 Oct, 2018 - Comments: 0

EDA and IP revenues were up across the board yet again, buoyed by growth across a number of new markets and an increase in new and existing companies developing chips for those markets. All told, revenue grew to $2.39 billion in Q2 of 2018, an 8.2% increase over the $2.21 billion reported in the same period in 2017, according to numbers released today by the ESD Alliance's Market Statistics ... » read more

RISC-V Inches Toward The Center
By Ann Mutschler - 01 Oct, 2018 - Comments: 1

RISC-V is pushing further into the mainstream, showing up across a wide swath of designs and garnering support from a long and still-growing list of chipmakers, tools vendors, universities and foundries. In most cases it is being used as a complementary processor than a replacement for something else, but that could change in the future. What makes RISC-V particularly attractive to chipmaker... » read more

Planning Out Verification
By Ed Sperling - 28 Sep, 2018 - Comments: 0

OneSpin Solutions’ Nicolae Tusinschi talks with Semiconductor Engineering about how to move from specification to signoff in a verification flow. https://youtu.be/2zrgaq2I1SQ » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy