category: System-Level Design

category: Auto, Security & Edge AI

Blog Review: Jan. 24
By Jesse Allen - 24 Jan, 2018 - Comments: 0

Mentor's Rich Edelman shares some tips for debugging complex UVM testbenches containing multiple agents, multiple checkers, and new HDL. Synopsys' Prasad Subudhi K. S. explains the PCIe PIPE 4.4.1 specification and the major improvements since 4.3, including better optimization in data flow and ultra-low power operations. Cadence's Paul McLellan steps back to before the Meltdown and Spect... » read more

eSilicon Builds ASIC Business On Leading-Edge Chip Design
By eSilicon - 24 Jan, 2018 - Comments: 0

This paper explores how advanced application specific integrated circuits (ASIC) chip design and manufacturing for leading-edge applications such as networking and artificial intelligence can be successfully outsourced. The company we profile is eSilicon, which has capabilities in 2.5D packaging, high-bandwidth memories (HBM), and silicon IP for fast memories and SerDes designs. The company ha... » read more

System Bits: Jan. 23
By Ann Mutschler - 23 Jan, 2018 - Comments: 0

Artificial synapse for “brain-on-a-chip” portable AI devices In the emerging field of neuromorphic computing, researchers are attempting to design computer chips that work like the human brain, which, instead of carrying out computations based on binary, on/off signaling like digital chips do today, the elements of a brain-on-a-chip would work in an analog fashion, exchanging a gradient of... » read more

The Week In Review: Design
By Jesse Allen - 19 Jan, 2018 - Comments: 0

M&A Barco Silex, now named Silex Inside, split from parent company Barco in a management buyout in partnership with a group of private investors lead by Dutch investment company Vehold BV. The company will continue its focus on security, video compression, and interface IP, along with design services. Tools & IP Mentor is making a version of its HyperLynx design rule checking tool ... » read more

Blog Review: Jan. 17
By Jesse Allen - 17 Jan, 2018 - Comments: 0

Mentor's Puneet Sinha identifies the key challenges, along with cost reduction and optimization opportunities, that come with using electric powertrains in autonomous vehicles. Synopsys' Robert Vamosi examines the impact of limited cellular networks on autonomous cars, and new communications protocols that could address coverage gaps. Cadence's Paul McLellan listens in as Lucian Shifren o... » read more

System Bits: Jan. 16
By Ann Mutschler - 16 Jan, 2018 - Comments: 0

Nitrogen-atom-sized sensors A new quantum sensor developed by Fraunhofer researchers will be able to measure the tiny magnetic fields of the next generation of hard discs, leveraging the new opportunities that quantum technology promises. [caption id="attachment_430671" align="aligncenter" width="300"] The special ellipsoid form of the plasma reactor developed at Fraunhofer IAF allows for l... » read more

EDA, IP Sales Up 8%
By Ed Sperling - 15 Jan, 2018 - Comments: 0

The EDA sector continues to exhibit solid growth, increasing 8% to $2.2262 billion in Q3, up from $2.0937 billion in the same period in 2016, according to the most recent stats from the ESD Alliance Market Statistics Service. The four-quarter moving average was up 11.5%, year over year. While all of the numbers were up, two areas showed extraordinary growth. One involved Japan, which showed ... » read more

The Week In Review: Design
By Jesse Allen - 12 Jan, 2018 - Comments: 0

M&A Synopsys acquired one-time programmable non-volatile memory IP provider Kilopass. Founded in 2001, Kilopass' 1T and 2T bitcell IP supports up to 4-Mbit OTP instances in 180-nm to 7-nm process technologies. The acquisition will add to Synopsys' growing OTP NVM portfolio: last October, Synopsys acquired Sidense, another provider of the technology. Terms of the deal were not disclosed. ... » read more

Blog Review: Jan. 10
By Jesse Allen - 10 Jan, 2018 - Comments: 0

Rambus' Aharon Etengoff explains the Meltdown and Spectre CPU vulnerabilities and why they could negatively affect the semiconductor industry for decades. Cadence's Paul McLellan has an explainer on Meltdown and how it's an unintended consequence of a processor behaving as intended. Mentor's Ruben Ghulghazaryan and Jeff Wilson investigate using machine learning to predict post-deposition ... » read more

Could Liquid IP Lead To Better Chips? (Part 3)
By Brian Bailey - 09 Jan, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

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