The Week In Review: Design


M&A Mentor acquired Valydate, provider of the VERA schematic integrity analysis tool. Founded in 2010, the Canadian company also offered signal and power integrity and static timing analysis services. Valydate's technology will be integrated with Mentor's Xpedition PCB design flow, though former Valydate CEO Michael Alam says it will continue to serve all EDA environments. Tools Aldec ... » read more

Blog Review: Aug. 9


Cadence's Paul McLellan digs into a recently discovered vulnerability in the Broadcom Wi-Fi chip used in many smartphones and why it should be a wakeup call for SoC designers. Mentor's Craig Armenti considers whether work-in-process design data management is an asset or a liability. Synopsys' Thomas M. Tuerke notes that in code, as in medicine, proper hygiene is should be treated as a con... » read more

IoT Security Requirements Ramping


By Haydn Povey The security issues associated with the Internet of Things are already well known. Whether it's bots infecting home networks, the destruction of industrial systems, or the ability to take remote control of automobiles, the horror stories are starting to mount like bodies in a bad movie. While legislating for security is never easy, and typically has proven imperfect, there is... » read more

System Bits: Aug. 8


Improving robot vision, virtual reality, self-driving cars In order to generate information-rich images and video frames that will enable robots to better navigate the world and understand certain aspects of their environment, such as object distance and surface texture, engineers at Stanford University and the University of California San Diego have developed a camera that generates 4D images... » read more

The Week In Review: Design


M&A Invecas will acquire Lattice Semiconductor's HDMI design team and Simplay Labs subsidiary, which oversees standards compliance and interoperability testing services. Invecas supplies foundation, analog, and interface IP optimized for GlobalFoundries processes. The deal is expected to close later this month. Last year, Lattice announced it would be acquired by Chinese private equity fir... » read more

Using Machine Learning In EDA


Machine learning is beginning to have an impact on the EDA tools business, cutting the cost of designs by allowing tools to suggest solutions to common problems that would take design teams weeks or even months to work through. This reduces the cost of designs. It also potentially expands the market for EDA tools, opening the door to even new design starts and more chips from more compan... » read more

Blog Review: Aug. 2


In a video, Cadence's Marc Greenberg describes the post-package repair capability in LPDDR4 and why it's important for future LP/DDR5 memories. Synopsys' Kiran Vittal looks at formal, machine learning, and when computers beat humans at games. Mentor's Matt Knowles digs into how cell-aware diagnosis works and why it can find tricky finFET defects. ARM's Freddi Jeffries digs into why com... » read more

CCIX Enables Machine Learning


It takes a lot of technology to enable something like machine learning, and not all of it is as glamorous as neural network architectures and algorithms. Several levels below that is the actual hardware on which these run, and that brings us into the even less sexy world of interfaces. One such interface, the Cache Coherent Interconnect for Accelerators (CCIX), pronounced C6, aims to make th... » read more

Data, Privacy And The IoT


The keynotes at this year's Design Automation Conference concentrated on the [getkc id="76" comment="Internet of Things"] (IoT). All of the speakers came from a hardware background, and thus all saw the benefits of being close to the system that is generating the data, providing the analytics, and producing some kind of action that provides the economic benefit. The alternative view comes f... » read more

The Week In Review: Design


IP Synopsys unveiled High Bandwidth Memory 2 (HBM2) IP. The package includes PHY, controller and verification IP and supports data rates up to 2400Mb/s, 20% faster than the JEDEC standard specification. The controller supports pseudo-channel operation in either lock step or memory interleaved mode, and the PHY offers four trained power management states and fast frequency switching. Cadence... » read more

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