category: System-Level Design

category: Auto, Security & Edge AI

The Week In Review: Design
By Jesse Allen - 13 Jan, 2017 - Comments: 0

M&A Synopsys acquired another code analysis company, Forcheck. A privately held software company based in the Netherlands, it provided a static analysis tool for detecting coding defects and anomalies in Fortran applications. Forcheck technology will be integrated into the Coverity tool. Terms of the deal were not disclosed. IP & Specifications Cadence launched verification IP ... » read more

Happy 25th Birthday, HAL!
By David Stork - 12 Jan, 2017 - Comments: 0

“Good afternoon, gentlemen. I am a HAL 9000 computer. I became operational at the H. A. L. plant in Urbana, Illinois on the 12th of January, 1992.”—Stanley Kubrick and Arthur C. Clarke, 2001: A Space Odyssey (1968). Nearly a half-century ago, Arthur C. Clarke and Stanley Kubrick introduced us to cinema’s most compelling example of artificial intelligence: the HAL 9000, a heuristicall... » read more

Blog Review: Jan. 11
By Jesse Allen - 11 Jan, 2017 - Comments: 0

Mentor's Ron Press examines why test hasn't become a bottleneck in creating ever more advanced semiconductors. Synopsys' Graham Etchells warns that while finFET technologies have been successful, challenges persist. Cadence's Paul McLellan shares a behind-the-scenes look at developing the Palladium Z1 emulator. The White House's Craig Mundie and Paul Otellini highlight a PCAST report o... » read more

System Bits: Jan. 10
By Ann Mutschler - 10 Jan, 2017 - Comments: 0

Speeding up computing tasks by turning memory chips into processors In a development that could lead to data being processed in the same spot where it is stored, for much faster and thinner mobile devices and computers, a team of researchers from Nanyang Technological University, Singapore (NTU Singapore), Germany’s RWTH Aachen University, and interdisciplinary research center Forschungszent... » read more

The Week In Review: Design
By Jesse Allen - 06 Jan, 2017 - Comments: 0

IP Arastu Systems uncorked a LPDDR3 DRAM Memory Controller. The controller is fully compliant with JEDEC standard JESD209-3C and supports various power down modes as well as multiple channels with a privilege to configure and manage each channel independently and parameterized data width. CSEM's Bluetooth Low Energy silicon RF IP has been validated as Bluetooth 5 compatible. RF test equip... » read more

Blog Review: Jan. 4
By Jesse Allen - 04 Jan, 2017 - Comments: 0

Mentor's Harry Foster wraps up his functional verification study series with a look the impact of verification maturity and safety critical designs on first silicon success. Synopsys' David Benas argues for using the insurance industry as a model in assessing the risk of potential software flaws. Cadence's Tom Anderson shares highlights from the recent International Workshop on Microproce... » read more

System Bits: Jan. 3
By Ann Mutschler - 03 Jan, 2017 - Comments: 1

Clues to high-temp superconductivity Offering clues about the microscopic origins of high-temperature superconductivity, physicists at Rice University’s Center for Quantum Materials (RCQM) have created a new iron-based material. The material is a formulation of iron, sodium, copper and arsenic created by Rice graduate student Yu Song in the laboratory of physicist Pengcheng Dai. The recip... » read more

Overcoming The Limits Of Scaling
By Ed Sperling - 29 Dec, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

Tech Talk: Timing Closure
By Ed Sperling - 29 Dec, 2016 - Comments: 0

Arteris' George Janac talks about timing closure issues in advanced chips and why this has reared its head again for the first time in a decade.   Related Stories Timing Closure Issues Resurface Adding more features and more power states is making it harder to design chips at 10nm and 7nm. » read more

Architect Specs Harder To Follow
By Ann Mutschler - 28 Dec, 2016 - Comments: 0

Interpreting and implementing architects' specifications is getting harder at each new process node, which is creating problems throughout the design flow, into manufacturing, and sometimes even post-production. Rising complexity and difficulties in scaling have pushed much more of the burden onto architects to deal with everything from complex power schemes, new packaging approaches, and to... » read more

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