category: System-Level Design

category: Auto, Security & Edge AI

Gluten-Free Virtual Prototyping
By Tom De Schutter - 24 Oct, 2014 - Comments: 0

When marketing products, should you emphasize what is included in the product or what is not? These days it seems that for so many foods it has become more important to highlight what is not in the food rather than what is. With sugar-free drinks, alcohol-free cocktails, gluten-free bread and dairy-free milk, one might wonder what you should continue to eat or drink. In fact, you now often see ... » read more

The Week In Review: Design
By Ed Sperling - 24 Oct, 2014 - Comments: 0

IP Cadence rolled out a portfolio of stacked die memory verification IP to support Wide I/O-2, Hybrid Memory Cube, high-bandwidth memory, and DDR4-3DS. Included are direct memory access for read, write, save, preload and comparison of memory contents, assertions, error configurability, and a built-in address manager. ARM rolled out additions to its enterprise-class SoC interconnects for qua... » read more

Redefining A System…And Why It Matters
By Ed Sperling - 23 Oct, 2014 - Comments: 0

The concept of a system on chip has been around since the mid-1990s, but the actual mass implementation of this scheme is almost synonymous with the rise of the smart phone over the past decade. Put in perspective, it isn't that old, and it's about to change. Prior to the [getkc id="81" kc_name="SoC"], an electronic system was largely a collection of components on a PCB that included memory,... » read more

Balancing The Cost Of Test
By Brian Bailey - 23 Oct, 2014 - Comments: 0

As semiconductor devices became larger and more complex, the cost of [getkc id="174" kc_name="test"] increased. Testers were large pieces of capital equipment designed to execute functional vectors at-speed and the technology being used had to keep up with increasing demands placed on them. Because of this, the cost of test did not decrease in the way that other high-tech equipment did. Around ... » read more

2.5D Timetable Coming Into Focus
By Ed Sperling - 23 Oct, 2014 - Comments: 0

After years of empty promises, the timetable for [getkc id="82" kc_name="2.5D"] is coming into better focus. Large and midsize chipmakers are behind it, real silicon is being developed, and contracts are being signed. That doesn't mean all of the pieces are in place or that market uptake is at the neck of the hockey stick. And it certainly doesn't mean the semiconductor industry is going to ... » read more

Why Is My Device Better Than Yours?
By Ed Sperling - 23 Oct, 2014 - Comments: 0

Differentiation is becoming a big problem in the semiconductor industry with far-reaching implications that extend well beyond just chips. The debate over the future of [getkc id="74" comment="Moore's Law"] is well known, but it's just one element in a growing list that will make it much harder for chip companies, IP vendors and even software developers to stand out from the pack. And withou... » read more

Advanced Nodes Drive Changing EDA Requirements
By Ann Mutschler - 23 Oct, 2014 - Comments: 0

With new technical requirements of today’s bleeding edge manufacturing processes propelling the ecosystem of semiconductor foundries, EDA tool suppliers and IP developers, work is being done behind the scenes like a well-conducted orchestra to make sure customer designs can flow through a foundry when the time comes. One of the areas in the design process where new processes are felt acute... » read more

How Many Levels Of Abstraction Are Needed?
By Jon McDonald - 23 Oct, 2014 - Comments: 0

Recently I was having a conversation with a user who was creating cycle accurate SystemC models. My initial thought was, "Why would this be necessary?" Through the course of discussions I realized that he did have a design questions that required that level of accuracy and the simulation performance trade-offs were appropriate for his needs. His cycle accurate SystemC models were running at abo... » read more

Changing The World, One Transaction At A Time
By Mike Gianfagna - 23 Oct, 2014 - Comments: 0

It’s the season for foundry seminars. A few weeks ago, eSilicon exhibited at the TSMC Open Innovation Platform event in San Jose. This week, we were at the GLOBALFOUNDRIES Technical Seminar, also in San Jose. I talked with a lot of folks during both events – recited the elevator pitch many times (“who is eSilicon?”). Everybody has attention deficit disorder on a tradeshow floor. Fast ex... » read more

A New Reuse Paradigm To Take 2.5D Packaging Technology Mainstream
By Jeff Scott - 23 Oct, 2014 - Comments: 0

With all of the recent product implementations and demonstrations of the technical viability of 2.5D technology, there is a lot of excitement around its potential. However, as with any new technology, there are concerns with cost and risk that limit mainstream adoption. Cost reduction and risk mitigation require some level of volume production, and therein lies a classic Catch-22. Is there a wa... » read more

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