category: System-Level Design

category: Auto, Security & Edge AI

Joe Costello To Get Back Into EDA?
By Brian Bailey - 31 Dec, 2013 - Comments: 3

While other writers in this world rely on gossip, there is a lot more that can come from hard work and paying attention. Perhaps one of the most famous and charismatic people from the EDA world is [getperson id="11147" p_name="Joe Costello"] – former CEO of [getentity id="22032" e_name="Cadence"] and still missed by many. Until recently he was CEO of a company called Orb Networks, a streamin... » read more

System Bits: Dec. 31
By Ann Mutschler - 31 Dec, 2013 - Comments: 0

Low signal loss waveguides With the potential to enable a leap ahead in size reduction and performance, DARPA-funded researchers at UCSB and CalTech have developed new methods to integrate long coils of waveguides with low signal loss onto microchips—potentially enabling a leap ahead in size reduction and performance. Long coils of optical waveguides—any structure that can guide light, ... » read more

When Is Verification Done?
By Ed Sperling - 20 Dec, 2013 - Comments: 0

Verification is becoming much more difficult at 16nm/14nm, driven by the sheer complexity of SoCs, the fact that there is much more to verify, and the impact of physical effects, which now affect what used to be exclusively the realm of functional verification. The questions these changes raise are daunting, and for many engineers rather unnerving. The whole validation, verification and debu... » read more

Plans Vs. Planning
By Jon McDonald - 20 Dec, 2013 - Comments: 0

The end of the year is a good time to look back at what’s happened over the past year, and look ahead to what might happen in the coming one. Two quotes that help my thought process when thinking about the might be coming, “Change is the law of life.” from Kennedy, and “Plans are nothing, but planning is indispensable” from Eisenhower. From my perspective, 2013 has been a good year... » read more

Week In Review: System-Level Design
By Ed Sperling - 20 Dec, 2013 - Comments: 0

Synopsys extended its FPGA prototyping board with a new version that is optimized for IP and subsystems. This is particularly interesting given the fact that Synopsys is one of the largest IP providers and currently sells subsystems based on its ARC processor IP. Among the new features are support for 4 million gates for software development and hardware-software integration, as well as synthes... » read more

Where Is 2.5D?
By Ed Sperling - 19 Dec, 2013 - Comments: 3

After nearly five years of concentrated research, development, test chips and characterization, 2.5D remains a possibility for many companies but a reality for very few. So what’s taking so long and why hasn’t all of this hype turned into production runs instead of test chips? Semiconductor Engineering spent the past two months interviewing dozens of people on this subject, from chipmakers ... » read more

Industry Restructures Around Cost
By Ed Sperling - 19 Dec, 2013 - Comments: 1

Talk to any semiconductor executive these days about what’s next for their company and you’ll probably encounter the same perspective—cost will drive future design decisions. Dig a little further, however, and you’ll find no consistent strategy for reducing that cost. While the industry has three very viable solutions for improving the power and performance characteristics of SoCs—... » read more

Executive Viewpoint: Bootstrapping A Startup
By Brian Bailey - 19 Dec, 2013 - Comments: 2

This story begins as many new developments have in the EDA industry. A designer, or verification person in this case, by the name of Yuan Lu, was working in a semiconductor company. He manually developed a lot of assertions for use in formal verification. He found they also were useful in a simulation environment, but he had great trouble convincing his fellow workers to develop similar ass... » read more

Making Modeling Less Unpleasant
By Brian Bailey - 19 Dec, 2013 - Comments: 1

How many times did your mother tell you to take your medicine? You knew two things: a) it would be unpleasant and b) it would be worth the few seconds of unpleasantness because of the benefits it would provide. It appears as if the electronics industry has the same issue with modeling. We talk about the benefits that having a system-level model would have — the ability to explore system archi... » read more

Patenting The Holidays
By Brian Bailey - 19 Dec, 2013 - Comments: 0

It happens every year — a new batch of [getkc id="16" kc_name="patents"] related to Christmas ornaments, things to rotate trees, or festive light controllers. Activity really did slow down this year with only six new [getkc id="98" kc_name="utility patents"] and five [getkc id="99" kc_name="design patents"] containing the word Christmas in their title, and a further two utility patents wit... » read more

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