Executive Briefing: 3D IC Stacking Challenges


Sonics CEO Grant Pierce sounds off on the challenges of stacking die, what has to change and why. [youtube vid=wCseVs738LQ] » read more

A Different Kind Of Design


Intel’s announcements at the Intel Developer Forum this week that it will be creating physically smaller packages that can run on far less energy raises some interesting questions about the future of all design. We’ve become accustomed to one-chip implementations, whether that’s a monolithic processor or an SoC with lots of processors. In the future, though, there may be multiple chips, a... » read more

Will Wide I/O Reduce Cache?


By Ann Steffora Mutschler In an ideal world, all new SoC technologies would make the lives of design engineers easier. While this may be true of some techniques, it is not the case with one advanced memory interface technology on the horizon, Wide I/O. There are claims that Wide I/O could reduce cache, but so far this is not widely understood. In fact, exactly how Wide I/O will be used, wha... » read more

The Age Of No-Spin Doctors


By Pallab Chatterjee Solid-state flash memory still isn’t cheap, but performance, reliability and power have transformed it from a niche market into a mainstream one. And it’s about to get even more popular. At the recent flash memory summit, the majority of the sessions focused on the further penetration of NAND flash into the consumer electronics product segment. NAND technology alrea... » read more

Wide I/O’s Impact On Memory


By Ann Steffora Mutschler Driven by the need to reduce power but increase bandwidth in smart phones and other mobile devices, system architects are grappling with new technologies to take system performance to the next level. Wide I/O, as well as some DDR technologies, are vying for center stage in tomorrow’s leading-edge mobile designs. “The big technological advancement that allows a ... » read more

Testing One, Two, Three


By Ed Sperling The rule of thumb at 90nm—still one of the mainstream process nodes—has been that test is something you do when a chip is done. You attach electrodes on either side, make sure the signal comes through clearly, and that the SoC functions properly. Try the same thing at 40nm, with multiple power islands, multiple voltage rails, lots of third-party IP and usually a slew of p... » read more

Mainstreaming


By Kurt Shuler Gartner analyst Jim Tully’s assessment that network on chip (NoC) technology will be “mainstream” in two to five years is an acknowledgement of the technical and commercial success NoC interconnect IP has had in the consumer electronics system on chip (SoC) market over the last couple of years. As reported by EE Times, Gartner’s latest “Hype Cycle for Semiconductors... » read more

Summertime…And The Living (Isn’t) Easy


By Jack Browne Normally summer is a time where most people slow down, relax, take vacations and the pace slows down accordingly with the seasonal ebb and flow of our industry. But not this summer. Exhibit A, B, C, D and so on: This past month has demonstrated the profound element of change. Mostly in our wallets. The stock market volatility and global economic disruptions have echoed (an... » read more

Which Came First?


By Jon McDonald Which came first the chicken or the egg? Based on some of my recent discussions I could ask the question in a slightly different way: “Which came first, the hardware or the software?” Depending on your point of view and personal bias the answer may appear obvious, but from what I've seen it can be very dependent on your current engineering situation. Adopting one perspectiv... » read more

Tech Talk: Graphic Headaches


Nvidia senior vice president of GPU engineering Jonah Alben talks with System-Level Design about the challenges of designing a graphics chip at advanced process nodes. [youtube vid=3Nc77aVH94g] » read more

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