category: System-Level Design

category: Auto, Security & Edge AI

Turning Chaos Into Order
By Jack Harding - 27 Apr, 2011 - Comments: 0

By Jack Harding It would be unthinkable to begin this article without recognition of the disaster the Japanese people are enduring, even as this is written. My friends and colleagues are as safe as they can be, so far; thousands are lost. But it takes no imagination to appreciate the psychological and very real overhang of nuclear toxins changing a society for a decade. The sad irony of the... » read more

What’s Missing In Verification
By Ed Sperling - 27 Apr, 2011 - Comments: 0

System-Level Design talks with Mentor Graphics, Cadence, and an Accellera member about what's changing in verification--and where the missing pieces are.   [youtube vid=alb3dncca4o] » read more

Effects Unknown
By Ed Sperling - 22 Apr, 2011 - Comments: 0

f you really want to know what’s going on inside the IC design world, pick up a copy of the annual reports of the largest foundries. Then triangulate that with the earnings reports of the largest makers of computers and mobile electronics and the makers of EDA tools and IP. All three areas are experiencing a massive uptick, which is good news considering the travails of the past couple of ... » read more

Behind The Analog Frenzy
By Ed Sperling - 08 Apr, 2011 - Comments: 0

Analog is suddenly very hot again, and much of it appears to be due to the promise of 2.5D and 3D stacking. Texas Instruments pulled out its checkbook to pay $6.5 billion for National Semiconductor, and Microsemi has offered $28 million for AML Communications, which makes low-noise and high-power microwave amplifiers. So what’s behind these move? In TI’s case, there appears to be a re... » read more

The Quest For A Better IP Integration Methodology
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling With the amount of IP in SoC designs now hitting an estimated 70% to 90%, companies are scrambling to figure out a way to more consistently integrate that IP and to test that it will work as expected. This is easier said than done, however, for a number of reasons: There are numerous types of IP, ranging from I/O to logic and memory. Not all IP is of equal quality. ... » read more

Fishing For Ideas In A Bigger Pond
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ann Steffora Mutschler From networking to optical modeling to open source software platforms, EDA engineers are drawing from a variety of disciplines to develop tools for chip design, stretching the technology beyond its original intent. To this end, Synopsys acquired Optical Research Associates (ORA) last fall to add optical design and analysis to its portfolio. The acquisition allowed ... » read more

Keeping Up With Complexity
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling There are two schools of thought in designing complex SoCs. One says that increasing complexity requires a higher level of abstraction. The other says providing enough detail to get the design right is the only effective way to do it. There are staunch proponents of both approaches, but what has been missing are bridges to tie the higher level of abstraction to the more labo... » read more

3D ICs: No Simple Answers
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Pallab Chatterjee Just how ready is the semiconductor industry for stacked die? That was the subject of a recent panel discussion involving ARM, Atrenta, Xilinx, Samsung and Mentor Graphics. The reasoning behind 3D stacking is becoming clearer at each node. I/O count and delay times are forcing different configurations, but the time frames for these changes and the gating constraints are... » read more

Moore’s Law Revisited
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling The push to 20nm and beyond is creating some interesting gyrations in the EDA industry. While tools vendors continue to work on tools for the latest process nodes, they’re also taking some significant sidesteps. The first to publicly recognize a shift is under way was Cadence, which last year issued its EDA 360 manifesto. The strategy is to continue investing in existing to... » read more

The Current State Of 3D Stacking
By Javier DeLaCruz - 31 Mar, 2011 - Comments: 0

By Javier DeLaCruz Thru-silicon-vias (TSVs) have become a very hot topic in in recent months. Ever since Xilinx reported that it is using a 2.5D TSV approach for its Virtex-7 FPGAs the industry started to salivate with the prospects of this new technology. While this technology may be accessible for larger stacked memory, FPGAs, MEMS devices, and CMOS image sensors, this does not inherently me... » read more

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