category: System-Level Design

category: Auto, Security & Edge AI

Financial Pressures Meet Chip Development
By Ed Sperling - 31 Oct, 2008 - Comments: 0

Decisions about what kinds of chips will be developed are changing, and not for the usual reasons. While there have always been technological challenges in developing semiconductors—many companies believed that 1 micron was the wall—business decisions are entering into the picture at a level never seen before. Some companies are running their chips for two process nodes instead of one—... » read more

OVM vs. VMM: What’s Next?
By Ed Sperling - 23 Oct, 2008 - Comments: 0

By Ed Sperling The lines are drawn. On one side stand Mentor Graphics and Cadence. On the other are Synopsys and ARM. And caught in the middle are verification engineers, with a preference for one or the other and often in mixed verification teams. The battle for dominance between the Verification Methodology Language (VMM) and the Open Verification Methodology (Open Verification Methodology)... » read more

Things You Never Knew About System Verilog
By Ed Sperling - 23 Oct, 2008 - Comments: 0

System Verilog is considered the current standard for a combined hardware description and verification language, and has been welcomed with open arms since it was approved by IEEE in 2005. Its usefulness in designing and verifying new chips is well known among those who work with it. The only problem is that many engineers still don’t know how to use more than a fraction of its capabilities�... » read more

Multicore Programming: The Next Frontier?
By Ed Sperling - 22 Oct, 2008 - Comments: 0

By Ed Sperling From a distance it looks like a game of hot potato. But this version is played by hardware and software engineers, who normally don’t have much to do with each other. The hardware engineers say you can’t get any more performance out of a single core on a chip without cooking it, so they’ve added more cores and tossed the problem over the wall to the software e... » read more

Verifying ASICs with FPGA Arrays
By Ed Sperling - 16 Oct, 2008 - Comments: 0

[youtube vid=pPNvvbCIzO4] » read more

What they don’t know…
By Ed Sperling - 08 Oct, 2008 - Comments: 0

  AMD’s spinoff of its fabs with a big cash infusion from investors in the United Arab Emirates is an indication of just how rotten things have become in the processor manufacturing business. AMD spent decades trailing one step behind Intel. When it finally caught up several years ago, using low-power as a selling point and bragging about better performance, Intel roared back to life a... » read more

Quality time?
By Ed Sperling - 08 Oct, 2008 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss the future of verification with Olivier Haller, design verification team leader for STMicroelectronics’ functional verification group; Hillel Miller, functional design and verification tools and methodology manager at Freescale; Kelly Larson, design verification engineering manager at MediaTek Wireless; Adnan Hamid, CEO of Breker, and ... » read more

Economic Bailout Meets Design
By Ed Sperling - 30 Sep, 2008 - Comments: 0

What does the economic bailout have to do with system-level design? Probably more than you’d guess. Convergence of the front and back end of chip design, combining everything from software with verification planning at the architectural level, is now being converged with one other element—business. And that business element is reaching far deeper than ever before. Business has always ha... » read more

What Else Can You Cram On A Chip?
By Ed Sperling - 16 Sep, 2008 - Comments: 0

Gordon Moore should be proud. At every process node, the number of transistors goes up, but so do the number of engineers you need to develop a chip. This may not be immediately obvious to anyone who’s actually working on a new chip. You’re probably part of a team that uses fewer engineers than several years ago, purchasing off-the-shelf IP blocks, and leaning heavily on design automatio... » read more

Cross-Talking with TLM 2.0
By Ed Sperling - 16 Sep, 2008 - Comments: 0

By Ed Sperling It’s almost like flying over the Great Plains of the United States. On the ground it’s hard to see above the corn stalks, but in an airplane you can see the entire horizon even if you can’t see those stalks anymore. The analogy is similar to where most of the major players in chip design say the engineering for systems on chips needs to go. With millions more gates avai... » read more

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