category: Technical Papers

category: Auto, Security & Edge AI

Step Towards 3D PICs: Low Loss Fiber-Coupled Interconnects (UIUC)
By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new technical paper titled "Low loss fiber-coupled volumetric interconnects fabricated via direct laser writing" was published by researchers at University of Illinois Urbana-Champaign (UIUC). Abstract "Photonic integrated circuits (PICs) are vital for high-speed data transmission. However, optical routing is limited in PICs composed of only one or a few stacked planes. Further, coupling ... » read more

NVMs: In-Memory Fine-Grained Integrity Verification Technique (Intel Labs, IISc)
By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new technical paper titled "iMIV: in-Memory Integrity Verification for NVM" was published by researchers at Intel Labs and Indian Institute of Science (IISc), Bengaluru. Abstract "Non-volatile Memory (NVM) could bridge the gap between memory and storage. However, NVMs are susceptible to data remanence attacks. Thus, multiple security metadata must persist along with the data to protect th... » read more

In Situ Backpropagation Strategy That Progressively Updates Neural Network Layers Directly in HW (TU Eindhoven)
By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new technical paper titled "Hardware implementation of backpropagation using progressive gradient descent for in situ training of multilayer neural networks" was published by researchers at Eindhoven University of Technology. Abstract "Neural network training can be slow and energy-expensive due to the frequent transfer of weight data between digital memory and processing units. Neuromorp... » read more

Monolithic 3D TFT Integration at Room Temperature, Used to Stack 10 Vertical Layers
By Technical Paper Link - 12 Jul, 2024 - Comments: 0

A new technical paper titled "Three-dimensional integrated metal-oxide transistors" was published by researchers at KAUST (King Abdullah University of Science and Technology). Abstract "The monolithic three-dimensional vertical integration of thin-film transistor (TFT) technologies could be used to create high-density, energy-efficient and low-cost integrated circuits. However, the develo... » read more

On-Chip Communication For Programmable Accelerators In Heterogeneous SoCs (Columbia, IBM)
By Technical Paper Link - 10 Jul, 2024 - Comments: 0

A technical paper titled “Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures” was published by researchers at Columbia University and IBM Thomas J. Watson Research Center. Abstract: "We present several enhancements to the open-source ESP platform to support flexible and efficient on-chip communication for programmable accelerators in het... » read more

Analysis Of The On-DRAM-Die Read Disturbance Mitigation Method: Per Row Activation Counting
By Technical Paper Link - 10 Jul, 2024 - Comments: 0

A technical paper titled “Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance” was published by researchers at ETH Zürich and TOBB University of Economics and Technology. Abstract: "We present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art on-DRAM-die read disturbance mitigation method, Per... » read more

Roadmap To Neuromorphic Computing (Collaboration of 27 Universities/Companies)
By Technical Paper Link - 09 Jul, 2024 - Comments: 0

A technical paper titled “Roadmap to Neuromorphic Computing with Emerging Technologies” was published by researchers at University College London, Politecnico di Milano, Purdue University, ETH Zurich and numerous other institutions. Summary: "The roadmap is organized into several thematic sections, outlining current computing challenges, discussing the neuromorphic computing approach, ana... » read more

RTL Optimization Via Verified E-Graph Rewriting (Intel, Imperial College London)
By Technical Paper Link - 08 Jul, 2024 - Comments: 0

A technical paper titled “ROVER: RTL Optimization via Verified E-Graph Rewriting” was published by researchers at Intel Corporation and Imperial College London. Abstract: "Manual RTL design and optimization remains prevalent across the semiconductor industry because commercial logic and high-level synthesis tools are unable to match human designs. Our experience in industrial datapath des... » read more

Programmable Quantum Emitter Formation In Si (Lawrence Berkeley National Lab., UC Berkeley)
By Technical Paper Link - 08 Jul, 2024 - Comments: 0

A technical paper titled “Programmable quantum emitter formation in silicon” was published by researchers at Lawrence Berkeley National Laboratory and University of California Berkeley. Abstract: "Silicon-based quantum emitters are candidates for large-scale qubit integration due to their single-photon emission properties and potential for spin-photon interfaces with long spin coherence t... » read more

Finely Tuning The Electronic Band Structure of WSe2 With AFM
By Technical Paper Link - 08 Jul, 2024 - Comments: 0

A technical paper titled “Strain Driven Electrical Bandgap Tuning of Atomically Thin WSe2” was published by researchers at University of Toronto, University of Tokyo,  and Stanford University. Abstract: "Tuning electrical properties of 2D materials through mechanical strain has predominantly focused on n-type 2D materials like MoS2 and WS2, while p-type 2D materials such as WSe2 remain... » read more

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