category: Top Stories

category: Auto, Security & Edge AI

Smaller Nodes, Much Bigger Problems
By Ed Sperling - 15 Jul, 2020 - Comments: 3

João Geada, chief technologist at Ansys, sat down with Semiconductor Engineering to talk about device scaling, advanced packaging, increasing complexity and the growing role of AI. What follows are excerpts of that conversation. SE: We've been pushing along Moore's Law for roughly a half-century. What sorts of problems are you seeing now that you didn't see a couple nodes ago? Geada: The... » read more

Maximizing Value Post-Moore’s Law
By Brian Bailey - 13 Jul, 2020 - Comments: 0

When Moore's Law was in full swing, almost every market segment considered moving to the next available node as a primary way to maximize value. But today, each major market segment is looking at different strategies that are more closely aligned with its individual needs. This diversity will end up causing both pain and opportunities in the supply chain. Chip developers must do more with a ... » read more

Moving Data And Computing Closer Together
By Bryon Moyer - 09 Jul, 2020 - Comments: 2

The speed of processors has increased to the point where they often are no longer the performance bottleneck for many systems. It's now about data access. Moving data around costs both time and power, and developers are looking for ways to reduce the distances that data has to move. That means bringing data and memory nearer to each other. “Hard drives didn't have enough data flow to cr... » read more

Designing For Extreme Low Power
By Brian Bailey - 09 Jul, 2020 - Comments: 3

There are several techniques available for low power design, but whenever a nanowatt or picojoule matters, all available methods must be used. Some of the necessary techniques are different from those used for high-end designs. Others have been lost over time because their impact was considered too small, or not worth the additional design effort. But for devices that last a lifetime on a si... » read more

Power Impact At The Physical Layer Causes Downstream Effects
By Ann Mutschler - 09 Jul, 2020 - Comments: 0

Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

What’s After PAM-4?
By Bryon Moyer - 23 Jun, 2020 - Comments: 1

[This is part 2 of a 2-part series. Part 1 can be found here.] The future of high-speed physical signaling is uncertain. While PAM-4 remains one of the key standards today, there is widespread debate about whether PAM-8 will succeed it. This has an impact on everything from where the next bottlenecks are likely to emerge and the best approaches to solving them, to how chips, systems and p... » read more

High-Speed Signaling Drill-Down
By Bryon Moyer - 17 Jun, 2020 - Comments: 0

Chip interconnect standards have received a lot of attention lately, with parallel versions proliferating for chiplets and serial versions moving to higher speeds. The lowliest characteristic of these interconnect schemes is the physical signaling format. Having been static at NRZ (non-return-to-zero) for decades, change is underway. “Multiple approaches are likely to emerge,” said Brig ... » read more

Interconnect Challenges Grow, Tools Lag
By Brian Bailey - 15 Jun, 2020 - Comments: 2

Interconnects are becoming much more problematic as devices shrink and the amount of data being moved around a system continues to rise. This limitation has shown up several times in the past, and it's happening again today. But when the interconnect becomes an issue, it cannot be solved in the same way issues are solved for other aspects of a chip. Typically it results in disruption in how ... » read more

Aging Problems At 5nm And Below
By Brian Bailey - 11 Jun, 2020 - Comments: 3

The mechanisms that cause aging in semiconductors have been known for a long time, but the concept did not concern most people because the expected lifetime of parts was far longer than their intended deployment in the field. In a short period of time, all of that has changed. As device geometries have become smaller, the issue has become more significant. At 5nm, it becomes an essential par... » read more

ESD Requirements Are Changing
By Bryon Moyer - 11 Jun, 2020 - Comments: 1

Standards for specifying a chip’s ability to withstand electrostatic discharge (ESD) are changing – in some cases, getting tougher, and in others, easing up. ESD protection has been on a path from a one-size-fits-all approach to one where a signal’s usage helps to determine what kind of protection it should get. Protecting chips from ESD damage has been a longstanding part of IC design... » read more

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