category: Top Stories

category: Auto, Security & Edge AI

Keeping Up With Complexity
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling There are two schools of thought in designing complex SoCs. One says that increasing complexity requires a higher level of abstraction. The other says providing enough detail to get the design right is the only effective way to do it. There are staunch proponents of both approaches, but what has been missing are bridges to tie the higher level of abstraction to the more labo... » read more

3D ICs: No Simple Answers
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Pallab Chatterjee Just how ready is the semiconductor industry for stacked die? That was the subject of a recent panel discussion involving ARM, Atrenta, Xilinx, Samsung and Mentor Graphics. The reasoning behind 3D stacking is becoming clearer at each node. I/O count and delay times are forcing different configurations, but the time frames for these changes and the gating constraints are... » read more

Moore’s Law Revisited
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling The push to 20nm and beyond is creating some interesting gyrations in the EDA industry. While tools vendors continue to work on tools for the latest process nodes, they’re also taking some significant sidesteps. The first to publicly recognize a shift is under way was Cadence, which last year issued its EDA 360 manifesto. The strategy is to continue investing in existing to... » read more

Memory, Bandwidth And SoC Performance
By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Ann Steffora Mutschler High-end SoC architectures today can contain dozens of processing engines—multiple cores from MIPS and ARM, DSPs from Tensilica and CEVA, and even graphics processors. But with so many cores there also is a need for enormous amounts of memory, and that has been creating some unexpected design problems, In many cases so much memory is required for an SoC that some... » read more

The Growing Importance Of Subsystems
By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Ed Sperling A growing reliance on third-party IP is beginning to expand well beyond just IP blocks and into full subsystems, opening significant growth opportunities for companies competing in this market as well as enormous business and technical challenges. The IP market is ripe for this kind of convergence. Complexity at advanced process nodes coupled with time-to-market demands has e... » read more

The Enterprise Effect
By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Pallab Chatterjee In the enterprise it’s all about speed and power—as in more speed and less power—and those changes are forcing shifts in the chip architectures as well as the processes used to develop those chips. At the Linley Data Center Conference the next generation of network control chips were discussed. The keys for the new networks are 10G data lanes to be used with 10G/4... » read more

Stuck In The Corners
By Ann Mutschler - 24 Feb, 2011 - Comments: 0

It’s common for semiconductor design teams to spend 60% to 70% of product development time on verification, which is why verification has bubbled to the top of the management chain as a concern. Executives worry about the predictability of their product development cycle because so much of it is dependent on successful execution of verification, the ability to achieve coverage closure and the... » read more

EDA Forecast: More Clouds
By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Ed Sperling Design engineers and EDA vendors used to scoff at the idea of cloud-based tools, but no one is scoffing anymore. A decade after the idea of renting tools online fell flat, largely due to security concerns by chipmakers, all three of the major EDA players and some smaller rivals are taking cloud-based solutions very seriously again. There are several reasons for this change... » read more

The Quest To Better Define Applications
By Ed Sperling - 27 Jan, 2011 - Comments: 0

By Ed Sperling For nearly five decades, just being able to get software to run on hardware and communicate with other systems was considered a feat of engineering. But with that part of the technology solved well enough, the next big challenge is to make sure that applications can run as efficiently as possible to maximize performance, minimize power consumption and limit the area required to ... » read more

Connecting System-Level Flows To Implementation Tools
By Ed Sperling - 27 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler With the complexity explosion occurring in SoC design today, there is a relentless force to push design decisions further up in terms of abstraction. Resolving issues at the gate level is not possible any more because there just isn’t enough time or resources. Further, the resulting design may not even be competitive because optimization at the gate level can leave ... » read more

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