category: Top Stories

category: Auto, Security & Edge AI

New 3D Stacking Techniques Emerge
By Ed Sperling - 16 Dec, 2010 - Comments: 0

By Pallab Chatterjee To take advantage of the capabilities of the new technologies, design and circuit architectures in the future will have to be closely coupled with the basic device creation. That shift was the subject of a special session at the recent IEDM conference focusing on the confluence of technology and design. One such area under discussion involved 3D ICs. While a lot of disc... » read more

The Rising Stake In Software Tools
By Ed Sperling - 03 Dec, 2010 - Comments: 0

By Ed Sperling The growing importance of software and off-the-shelf IP in semiconductor design is beginning to change the dynamics of the entire EDA tools business, setting off a string of acquisitions as the largest players realign themselves to take advantage of this shift. The most recent example: Mentor Graphics’ acquisition this week of CodeSourcery, a GNU-based Linux toolchain and s... » read more

Standards Update
By Ann Mutschler - 18 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler In the sometimes-murky waters of system-level modeling standards where real-world adoption can be difficult to track, work is progressing to help hardware and software engineers realize the promise of true hardware-software codesign. The three main standards efforts related to modeling at the system level are OSCI’s TLM-2.0, OCP-IP’s OCP and Open Modeling TAB a... » read more

Reducing Bottlenecks
By Ann Mutschler - 18 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler For the first time ever, China recently earned fastest supercomputer bragging rights with its Tianhe-1A supercomputer, which can perform 2.57 quadrillion computing operations per second. The machine has been successfully used to survey mines, forecast weather and design high-end machinery. While it has caused concern, it is important to note that the Tianhe-1A use... » read more

Building Up In 3D
By Ed Sperling - 18 Nov, 2010 - Comments: 0

By Ed Sperling Stacked die are expected to begin showing up in volume in late 2012 and in 2013, turning what has been a science experiment into a mainstream way of designing and manufacturing SoCs. This magnitude of this shift cannot be overstated, and clearly all of the pieces are not in place to make it all happen immediately. There also are significant technology challenges to overcome, ... » read more

Verifying At The System Level
By Ed Sperling - 18 Nov, 2010 - Comments: 0

By Ed Sperling Verification has always been the problem child of SoC design. It requires the most engineering resources, the largest block of time and the biggest budget in the design process. And at each new process node the problem gets bigger, in part because there is more stuff on each die—transistors, memory, interconnects, I/O, functionality—and in part because chipmakers are being c... » read more

Best Practices For Multicore SoC Test And Debug
By Ann Mutschler - 21 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler In increasingly complex SoC designs, many of which contain multiple cores and multiple modes, determining best practices for testing and debugging is a moving target. Jason Andrews, architect at Cadence Design Systems, said multicore debug is a huge issue. It isn’t easy to do, and there aren’t many good ways to do it. He suggested one approach is to try to u... » read more

The Growing Need For Concurrent Design
By Ed Sperling - 21 Oct, 2010 - Comments: 0

By Ed Sperling The move toward concurrent design is escalating at advanced nodes, driven more by the need to ensure that everything works than previous efforts aimed at efficiency and time-to-market. While the concept has surfaced before in limited doses—engineers and EDA companies have been talking about doing more things simultaneously for the better part of a decade—there are some in... » read more

The Future Of 3D Stacking
By Ed Sperling - 21 Oct, 2010 - Comments: 0

By Ed Sperling Despite concerns about the lack of tools, an unstable process, questionable interconnects, thermal overloads and electrostatic discharge, 3D stacking appears to be making headway. At the very least, lots of companies of all sizes are betting heavily that it will succeed. The first wave, which is expected to start showing up late next year, will likely come from a handful of t... » read more

Bridging IP With Verification Standards
By Ann Mutschler - 21 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT -- IEEE 1685, "Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” – with verification IP. The IP-XACT technical committee has been busy over the past year. Formerly an effor... » read more

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