Intelligent Verification Offers Hope For “Smartening” Up Verification


By Cheryl Ajluni As with death and taxes, when it comes to design some things are just inevitable. For one, as design geometries shrink, design complexity will continue to increase. For another, verification is the single most time-consuming and intensive part of the entire design cycle. While new tools and methodologies have enabled designers to work through many of the existing complexity i... » read more

Soft Errors Create Tough Problems


By Ed Sperling Single event upsets used to be as rare as some elements on the Periodic Table, with the damage they could cause relegated more to theory than reality. Not anymore. At 90nm, what was theory became reality. And at 45nm, the events are becoming far more common, often affecting multiple bits in increasingly dense arrays of memory and now, increasingly, in the logic. Known alter... » read more

Moore’s Law Splinters


By Ed Sperling Moore’s Law continues progressing at a rate of one node every two years or so, but the number of companies that are adhering to that schedule is becoming much harder to pinpoint. Even the nodes themselves are becoming fuzzy. While Intel is looking at 32nm as the next node after 45nm, TSMC is looking at 28nm as the next node after 40nm. And there are likely to be extensions wi... » read more

Easing System Creation With Embedded Hardware Solutions And Standards


By Cheryl Ajluni System creation is today an ultra-complex task. On one hand, developers are confronted with consumer demands for ever more functionality, better performance and increased power efficiency at a lower cost. On the other hand, they face stringent time-to-market requirements and changing standards, coupled with the need to accommodate a range of requirements pertaining to differen... » read more

Exclusive Research: What’s Happening With Third-Party IP


Analog and mixed signal IP began closing the gap with digital core IP in design explorations in the first two months of this year, a clear sign that multicore systems on chip have emerged as the dominant semiconductor model and that the architecture requires both types of IP. While it’s too early to tell this year what effect that will have on overall design activity—the economy is the rea... » read more

Taming The Multicore Beast


By Ed Sperling Multicore chips are here to stay. Now what? That question is echoing up and down the ranks of tools vendors, design engineers, software developers and even among people who measure the performance and efficiency of semiconductors. There is now a Multicore Expo and a Multicore Association that includes a who’s who of electronics. And there are lots of working groups developing... » read more

Thinking Digital To Design Analog, And Vice Versa


By Ed Sperling Until several years ago, analog was a world apart from digital. Analog engineers could comfortably avoid many of the issues of Moore’s Law, viewing it as a costly bad habit with an equally bad outcome. Most analog engineers gloated privately that they could still develop chips at 250nm, or at worst 130nm, while their digital counterparts were struggling to keep up with is... » read more

Exploring The Use Of Virtual Platforms At The Electronic System Level


By Cheryl Ajluni System design is hard. That should not come as a surprise to anyone these days. With design geometries shrinking and device complexity on the rise, this fact is not likely to change anytime soon. One concept for easing that burden for system-level designers is the virtual platform. Granted, the concept itself is nothing new, but today it is being employed in ever more creativ... » read more

Trends in System-Level Prototyping


By Clive Maxfield One problem with electronics is that certain terms can mean different things, depending on who one is talking to at the time. Even worse, some terms have a tendency to evolve over time. This means that when we are presented with a topic like "Trends in System-Level Prototyping," before leaping headfirst into the fray, it may be a good idea to first define exactly what we mean... » read more

NoC Your SoCs Off


By Ed Sperling The network on a chip (NoC) approach is gaining ground as an essential part of a system on a chip (SoC), providing the same kind of time-to-market advantage that well-tested intellectual property blocks provide. This follows almost eight years of hype about NoCs potential with little to show for it. Times have changed and there appear to be two main drivers, one technological a... » read more

← Older posts Newer posts →