High-Level Gaps Emerge


Semiconductor Engineering sat down to discuss the attributes of a high-level, front-end design flow, and why it is needed at present with Leah Clark, associate technical director for digital video technology at [getentity id="22649" e_name="Broadcom"]; Jon McDonald, technical marketing engineer at [getentity id="22017" e_name="Mentor Graphics"]; Phil Bishop, vice president of the System Level D... » read more

More Than Moore


Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

Where Do We Stand With CDC


Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of [getentity id="22674" e_name="Arteris"]; Shaker Sarwary, VP of Formal Verification Products at [getentity id="22026" e_name="Atrenta"]; Pranav Ashar, CTO at [getentity id="22416" e_name="Real Intent"]; and Namit Gupta, CAE, Verification Group at [getentity id="22035" e_nam... » read more

The Real Numbers: Redefining NRE


Developing ICs at the most advanced nodes is getting more expensive, but exactly how much more expensive is the subject of debate across the semiconductor industry. There are a number of reasons for this discrepancy. Among them: As design flows shift from serial to parallel, it's hard to determine which groups within companies should be saddled with different portions of the bill. The re... » read more

How To Cut Verification Costs For IoT


Cost is one of the main factors limiting proliferation of the [getkc id="76" comment="Internet of Things"] (IoT), and when looking at the design and [getkc id="10" kc_name="Verification"] methodologies in place today, verification is a prime candidate for closer inspection. For today’s complex [getkc id="81" kc_name="SoCs"], the cost of verification has been rising faster than design and it h... » read more

Challenges Increase for IP At Advanced Nodes


At advanced process nodes such as 16/14/10nm, designing [getkc id="43" comment="IP"] is a much tougher nut to crack due to complexity and other considerations, not to mention then trying to migrate and/or re-use that IP. Still, engineering teams are looking for leverage wherever they can find it in their designs amid the technical challenges to overcome. Tomasz Wojcicki, vice president of c... » read more

IoT Demands Correct By Construction Assembly


The article Limiters To The Internet Of Things outlined several factors that are slowing the rate of deployment for the [getkc id="76" kc_name="IoT"]. Those limiters are cost, power delivery and storage, standards, security, and the limits of your imagination. This article picks up on a comment made by [getperson id="11244" comment="Chris Rowen"], fellow at [getentity id="22032" e_name="Cadence... » read more

Productivity And The IoT


The market for devices that connect almost everything to the [getkc id="76" comment="Internet of Things"] is projected to explode, creating opportunities for companies that haven’t been traditional chip developers to decide to start developing devices. Semiconductor Engineering sat down to discuss this topic with Jack Guedj, corporate VP of Tensilica products at [getentity id="22032" e_name="... » read more

Time To Market Concerns Worsen


Time to market has always been an issue for chipmakers in highly competitive sectors, but as complexity of chips continues to grow at advanced nodes, and as markets shift increasingly toward consumer electronics, it has jumped to the No. 1 concern. Interviews with engineers at multiple levels inside of some of the largest and midsize chipmakers, conducted by Semiconductor Engineering over th... » read more

Executive Insight: Lip-Bu Tan


Semiconductor Engineering sat down with [getperson id="11693" comment="Lip-Bu Tan"], president and CEO of [getentity id="22032" e_name ="Cadence"], to discuss his outlook on EDA, Moore’s Law and his strategy for investing in startups around the world. What follows are excerpts of that conversation. SE: What’s worrying you these days? Tan: There are a couple of things. One is the complex... » read more

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