category: Top Stories

category: Auto, Security & Edge AI

More Than Moore
By Ed Sperling - 15 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

Stacked Die Politics, Technology And Tools
By Ed Sperling - 08 Sep, 2014 - Comments: 0

The path to stacking die may look fairly straightforward, but reality is somewhat different. There is a battle raging between foundries and OSATs over who will actually stack and package the die. There is new technology being created that could change the economics of how these die go together. And there is debate about just how ready the tools are to make all of this happen. All of this is ... » read more

Fixing Functional Coverage
By Brian Bailey - 22 Aug, 2014 - Comments: 2

Constrained random test pattern generation entered the scene a couple of decades ago as a better way to spend time and resources for the creation of stimulus. Stimulus definition had become an arduous task—defining the patterns necessary to exercise designs of increasing size. It was successfully argued that spending time writing models instead of creating stimulus and having a computer p... » read more

Looking For The Next Big Thing
By Brian Bailey - 21 Aug, 2014 - Comments: 0

With [getkc id="74" comment="Moore's Law"] slowing down or coming to an end, finding the next big thing may be very different than it was in the past. We cannot assume that more of the same will be a winner. The semiconductor industry has been blessed with two new product categories that have catapulted it through what should have been a very difficult period with barely a scratch. Those techno... » read more

The Changing IP Ecosystem
By Ann Mutschler - 21 Aug, 2014 - Comments: 0

Is a larger [getkc id="43" kc_name="IP"] company better suited to deliver what users need – from hardware to software to PDKs and reference designs – with larger and more diverse teams to draw upon, as well as deep foundry relationships? Or does it pay to small, quick and nimble? The answer to that question appears to be playing out in real time. As design complexity has increased, so ha... » read more

More Than Moore
By Ed Sperling - 21 Aug, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at Open-Silicon; Patrick Soheili, vice president and general manager of IP Solutions at eSilicon; Brandon Wang, engineering group director at Cadence; John Ferguson, product manager for DRC applications at Mentor Graphics; and Kevin Kranen, d... » read more

IP Subsystems: What Works, What Doesn’t
By Ann Mutschler - 21 Aug, 2014 - Comments: 0

The [getkc id="81" kc_name="SoC"] landscape has changed substantially over the past decade and so have some of the definitions for aspects of the system—particularly the [getkc id="43" kc_name="IP"] subsystem. “We’ve been at the point for some time for large SoCs that what we thought about as a building block 10 years ago is now too small,” said [getperson id="11489" p_name="Drew Win... » read more

Different Approaches Emerge For Stacking Die
By Ed Sperling - 21 Aug, 2014 - Comments: 1

The concept of stacking die to shorten wires, improve performance, and reduce the amount of energy required to drive signals has been in research for at least the past dozen years at both IBM and Intel. And depending upon whom you ask, it could be another 2 to 10 years before it becomes a mainstream packaging approach—if it happens at all. At least part of the confusion stems from how you ... » read more

Executive Insight: Jack Harding
By Ed Sperling - 18 Aug, 2014 - Comments: 0

SE: What’s worrying you these days? Harding: One thing that bothers me is the cost of chip development on a per-chip basis. We seduce ourselves into thinking everything is wonderful because the cost per transistor is dropping in chunks. Gate costs are going down at every node. If you look at the secular trend, we’ve done a pretty good job putting a lot of stuff in a small space. In my bu... » read more

Executive Insight: Taher Madraswala
By Ed Sperling - 11 Aug, 2014 - Comments: 1

Semiconductor Engineering sat down with Taher Madraswala, president of Open-Silicon, to talk about future challenges, opportunities and changes. What follows are excerpts of that interview. SE: What worries you most? Madraswala: What worries me at the industry-level is the growing effect that business constraints are having on product innovation. We’ve done a very good job of advancing ... » read more

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