category: Top Stories

category: Auto, Security & Edge AI

The Evolving Interconnect
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Chip interconnect protocol requirements are evolving as designs move to 20nm and below process geometries, and not always in predictable ways. At least part of this is being driven by what an SoC is used for. The continued push to shrink features opens up real estate at each new process node. For the past decade, that real estate has been used to add more featu... » read more

The Smartphonification Of Things
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler The term, ‘Internet of Things,’ was first coined more than a decade ago by technology visionary Kevin Ashton but has slowly trickled down to the world of chip design and is now mentioned constantly in conversation. The reason is simple: System-level design tools are getting sophisticated enough to handle the intricacies required by devices in an Internet of ... » read more

More Than Data Management
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Managing the people, the data and the technology are just as important as meeting the market window given that without these, the entire project wouldn’t function. Throw huge data set sizes, different cultures and business management issues into the mix and the challenges are many. Fortunately, these are issues that the semiconductor industry has been refining for ... » read more

Continuous, Connected And Concurrent Verification
By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling It’s a wonder that any electronic system works as intended, or that it continues to work months or years after it is sold. The reason: SoCs have become so complex that no verification coverage model is sufficient anymore, no methodology covers every aspect of verification, and no single tool or even collection of tools can catch every bug or prevent them from being there in th... » read more

Verifying Your Intent
By Ann Mutschler - 21 Mar, 2013 - Comments: 0

Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before manufacturing. Checking electrical characteristics of a design is one thing. Verifying power intent is quite another. And the overlap of the two is an intriguing concept. Case in point: Checking fo... » read more

Smarter Things
By Ed Sperling - 28 Feb, 2013 - Comments: 0

By Ed Sperling SoC design has largely been a race to the next process node in accordance with Moore’s Law, but it’s about to take a sharp turn away from that as the Internet of Things becomes more ubiquitous. There has been much made about the Internet of Things over the past couple of years—home networks that involve smart refrigerators sending reminders to consumers that the milk is... » read more

Mythbusting: Co-Design
By Ed Sperling - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler It turns out that while there needs to be understanding between hardware and software engineers, the people doing the programming don’t actually want or need to interact. There is not, nor probably ever will be, one single team with hardware and software engineers happily working together on a project. But it’s not a total disconnect. There are a number o... » read more

The New Platform-Based Design
By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Driven by the continued explosion in design costs, the term ‘platform-based design’ is evolving. A platform used to be viewed as an actual chip with some configurability on it that a semiconductor company promoted. Their customers would buy that chip in volume, configure it to their requirements, and sell it inside their end devices. The definition has beco... » read more

The Rise Of Layout-Dependent Effects
By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Designing for today’s advanced semiconductor manufacturing process nodes brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Layout-dependent effects (LDE), which emerged at 40nm and are having a larger impact at 28 and 20nm, introduce variability to circuit ... » read more

Surprises Abound As Subsystem IP Gains Prominence
By The SE Staff - 28 Feb, 2013 - Comments: 0

What’s new in the world of subsystem intellectual property? To find out, System-Level Design sat down with Richard Wawrzyniak, senior market analyst for ASICs and SoCs at Semico Research Corp. What follow are excerpts of that conversation. SLD: You mentioned that the cost of semiconductor intellectual property (IP) at 20nm and below is increasing. Why is that? Wawrzyniak: The reason is c... » read more

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