SoC Architects Face Big Challenges


By Ann Steffora Mutschler While the geometries of advanced node processes such as 28nm and below may not greatly impact SoC architectures, the complexity enabled by the leading edge brings intense challenges all the same. With the ability to put more transistors onto a chip come new possibilities such as the increasing use of multi-core architectures and lots of integrated hardware en... » read more

Inside The System-Level Supply Chain


System-Level Design sat down to discuss supply chain issues with Bill Chown product marketing director for the system-level engineering division at Mentor Graphics and a longtime participant in a number of standards efforts across the semiconductor design industry. What follows are excerpts of that conversation. SLD: What’s happening with system engineering as chip design/manufacturing mo... » read more

Mixing It Up


By Ann Steffora Mutschler To enable the next level of productivity in the verification space, certain tools need to be combined and integrated in a very meaningful way. The concept is far from new. This happened on the RTL to GDS front between synthesis and place and route. The tools work very closely and there is bi-directional collaboration. It also happened in the functional verification... » read more

Cost Per Transistor Gets Fuzzier


By Ed Sperling Cost per transistor always has been a major reason for chipmakers to migrate to the next process node. By shrinking transistors and adding more logic, performance usually gets a boost. Moreover, that usually provides enough engineering wiggle room to add some improvements in energy efficiency. The basic assumption that you can double the number of transistors every 24 months,... » read more

Changes In The Supply Chain


Runaway complexity in design, implementation, verification and manufacturing is being mirrored across an increasingly complex supply chain. Now the question is what to do about it. Complexity is being driven by the continued shrinking of feature sizes and the clamor for more functionality to leverage the real estate that becomes available with each new process node. But the increased density... » read more

What Happened To Statistical Static Timing Analysis?


About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA). Fast forward to now and the industry seems to have put this approach on the back burner. So what happened? “The idea was that if you modeled your design instead of using a corner-based approa... » read more

Adventures In Verification


By Ed Sperling Design complexity can be almost bit-mapped with verification complexity. There are so many things that need to be verified in a design these days that full coverage has become almost possible to guarantee. That has created a market for tools to help with the verification process—formal, functional, physical—and different methodologies for using those tools. But how to app... » read more

What’s Ahead For System-Level Design


By Ann Steffora Mutschler Architecting an SoC today is incredibly difficult. When you add in the number of available transistors, the manufacturing effects of smaller nodes, IP and software that must be integrated, among other things, the challenges just keep mounting. Depending on what market segment the SoC will be designed into has a huge impact, as well. “It is impossible to ove... » read more

Taking Stock Of Models


By Ann Steffora Mutschler The world of modeling in SoC design is multi-dimensional to say the least. One dimension contains the model creators and providers, while the other is comprised of the types of models that exist in the marketplace. “What we’re seeing today is that we have basically models coming from either IP providers—the people that are actually producing those cores ... » read more

Executive Outlook


By Ed Sperling The view from the top of companies is a like a high-level of abstraction for viewing the industry. While engineers get caught up in individual projects, or pieces of projects, CEOs and CTOs tend to see things from a much broader perspective. So what do they see as the big issues and developments over the next 12 to 24 months? System-Level Design asked industry leaders that q... » read more

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