category: Top Stories

category: Auto, Security & Edge AI

Verification Unification
By Brian Bailey - 25 May, 2017 - Comments: 0

There is a lot of excitement about the emerging [getentity id="22028" e_name="Accellera"] [getentity id="22863" e_name="Portable Stimulus”] (PS) standard. Most of the conversation has been about its role in [getkc id="11" kc_name="simulation"] and [getkc id="30" kc_name="emulation"] contexts, and in the need to bring portability and composability into the verification flow. Those alone are st... » read more

Samsung Unveils Scaling, Packaging Roadmaps
By Ed Sperling - 24 May, 2017 - Comments: 5

Samsung Foundry unveiled an aggressive roadmap that scales down to 4nm, and which includes a fan-out wafer-level packaging technology that bridges chips in the redistribution layer, 18nm FD-SOI, and a new organizational structure that allows the unit much greater autonomy as a commercial enterprise. The moves put [getentity id="22865" e_name="Samsung Foundry"] in direct competition with [get... » read more

Reworking Established Nodes
By Ed Sperling - 24 May, 2017 - Comments: 2

New technology markets and a flattening in smartphone growth has sparked a resurgence in older technology processes. For many of these up-and-coming applications, there is no compelling reason to migrate to the latest process node, and equipment companies and fabs are rushing to fill the void. As with all electronic devices, the focus is on cost-cutting. But because these markets are likely ... » read more

Whatever Happened To HLS?
By Brian Bailey - 24 May, 2017 - Comments: 1

A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high-lev... » read more

The Race To 10/7nm
By Mark LaPedus - 22 May, 2017 - Comments: 4

Amid the ongoing ramp of 16/14nm processes in the market, the industry is now gearing up for the next nodes. In fact, GlobalFoundries, Intel, Samsung and TSMC are racing each other to ship 10nm and/or 7nm technologies. The current iterations of 10nm and 7nm technologies are scaled versions of today’s 16nm/14nm finFETs with traditional copper interconnects, high-k/metal-gate and low-k diele... » read more

200mm Crisis?
By Mark LaPedus - 18 May, 2017 - Comments: 7

Over the last year or so, the IC industry has experienced an acute shortage of both 200mm fab capacity and 200mm equipment amid a surge of demand for certain chips. Right now, though, the 200mm shortfall is much worse than before. But this situation isn’t expected to improve for both elements in the second half of 2017, and perhaps beyond. On the capacity front, chipmakers are generally... » read more

Extending EUV Beyond 3nm
By Ed Sperling - 18 May, 2017 - Comments: 10

Jan van Schoot, senior principal architect at [getentity id="22935" comment="ASML"], sat down with Semiconductor Engineering to talk about how far EUV can be extended and where it is today. What follows are excerpts of that discussion. SE: High numerical aperture [gettech id="31045" comment="EUV"] has been in the works for some time as a way of extending EUV. How is this technology shaping... » read more

Materials For Future Electronics
By Katherine Derbyshire - 18 May, 2017 - Comments: 0

Examining the research underway in electronics materials provides a keyhole view into what may be possible in future electronics design. Although some of this research will not end up in commercial products, it does provide an indication of the kinds of problems that are being addressed, how they are being approached, and where the research dollars are being spent. Flexible electronics are a... » read more

Maintaining Power Profiles At 10/7nm
By Ann Mutschler - 17 May, 2017 - Comments: 0

Understanding power consumption in detail is now a must-have of electronic design at 10nm and below, putting more pressure on SoC verification to ensure a device not only works, but meets the power budget. As part of this, the complete system must be run in a realistic manner — at the system-level — when the design and verification teams are looking at the effects of power during hardwar... » read more

Whatever Happened to High-Level Synthesis?
By Brian Bailey - 16 May, 2017 - Comments: 0

A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high lev... » read more

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