category: Top Stories

category: Auto, Security & Edge AI

Hardware Accelerators Earn Their Keep
By Ann Mutschler - 08 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler Hardware accelerators have been used for years, but with the proliferation of multicore chips and SoCs their use is evolving. Multicore processors have reduced the reliance on hardware accelerators, but that doesn’t mean the number of hardware accelerators is shrinking. The insatiable demand for performance while also reducing power consumption means that acceler... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 08 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate app... » read more

Too Big To Handle?
By Ann Mutschler - 08 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler With the insatiable demand for power efficiency today, the power management tasks have been pushed up into the realm of the software engineer due to the sheer complexity of the hardware design and the demands on the hardware designer to get their part right. Managing power properly in embedded software boils down to really understanding the application and how it i... » read more

How Secure Is Your SoC?
By Ed Sperling - 07 Aug, 2013 - Comments: 0

The Russian Federal Guard Service’s decision to revert to typewriters—machines that leave unique mechanical fingerprints—is a good indicator of just how serious security has become in a world dominated by electronics and pervasive connectivity. What’s less apparent is the growing threat at the SoC level—inside complex chips, between the chip and the board, and between chips on the ... » read more

Experts At The Table: Performance Analysis
By Ed Sperling - 02 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Ravi Kalyanaraman, senior verification manager for the digital entertainment business unit at Marvell; William Orme, strategic marketing manager for ARM’s System IP and Processor Division; Steve Brown, product marketing and business development director for the systems and software group at Cadence; Johannes Stahl director o... » read more

Experts At The Table: Automotive Electronics
By Ann Mutschler - 02 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss the opportunities in automotive electronics with Alexandre Palus, principal SoC architect at Altera; Aveek Sarkar, VP of product engineering & support at Apache; Mladen Nizic, engineering director, mixed signal solution at Cadence; and Stephen Pateras, product marketing director, silicon test solutions at Mentor Graphics. W... » read more

3D IC Supply Chain: Still Under Construction
By Barbara Jorgensen - 25 Jul, 2013 - Comments: 1

By Barbara Jorgensen and Ed Sperling Stacked die, which promise high levels of integration, a tiny footprint, energy conservation and blinding speed, still have some big hurdles to overcome. Cost, packaging and manufacturability continue to make steady progress, with test chips being produced by all of the major foundries. But in a disaggregated ecosystem, the supply chain remains a big st... » read more

New Silos Form In IC Industry
By Ed Sperling - 25 Jul, 2013 - Comments: 0

By Ed Sperling For the past couple of decades corporations around the globe have been focused on down silos. In fact, it has become a mantra. It’s considered essential for making established corporations even more successful, and it’s almost always at the center of turnaround plans for troubled companies. Moreover, across a full spectrum of companies, it’s regularly cited by management c... » read more

Measuring Verification Productivity
By Ann Mutschler - 25 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler In this era of mammoth SoCs that require the utmost in verification complexity, it’s not enough to have a methodology. Design and verification teams also need to measure their productivity to constantly stay ahead of the curve. The more sophisticated customers are measuring a lot of things, explained Steve Bailey, marketing director at Mentor Graphics, “and for... » read more

GPUs May Speed UP EDA Algorithms
By Ann Mutschler - 25 Jul, 2013 - Comments: 1

The sequential EDA algorithms of old cannot keep pace with increasing design complexity, which is driving the industry to look at parallelism and other computational architectures such as the graphical processing unit (GPU). A 10X or 20X speedup for gate-level simulations means that a test that runs today in a week will run in less than a day, and a test that runs today in a month will run i... » read more

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