category: Top Stories

category: Auto, Security & Edge AI

Raising The IP Abstraction Level
By Ed Sperling - 25 Jul, 2013 - Comments: 0

By Ed Sperling An increasing reliance on commercial and re-used IP and more emphasis placed on software development is adding even more pressure onto semiconductor design teams to figure out the benefits and limitations of myriad possible choices earlier in the design process. Design teams already are under pressure to meet increasingly tighter market deadlines, and it is stressing every pa... » read more

A Tale Of Two Standards
By Ed Sperling - 18 Jul, 2013 - Comments: 0

By Ed Sperling It could well be one of the strangest developments in standards history. Two competing standards for power formats were rolled out in the middle of the last decade and aside from a few cries of foul they fell below the radar screen of most chip designers and architects for a half-dozen years. Fast forward to the present and the Common Power Format (CPF) and Unified Power Form... » read more

Foundries Eye 300mm Analog Fabs
By Mark LaPedus - 18 Jul, 2013 - Comments: 0

By Mark LaPedus In 2009, Texas Instruments changed the semiconductor landscape when it opened the industry’s first 300mm fab for analog chips. Until then, analog chip production was conducted in fabs at 200mm wafer sizes and below. With a 300mm fab, TI potentially could gain a die-size and cost advantage over its analog rivals. On paper, a 300mm wafer provides 2.5 times more chips than a... » read more

High NA EUV Litho May Require Larger Photomask Size
By Jeff Chappell - 18 Jul, 2013 - Comments: 0

By Jeff Chappell With extreme ultraviolet lithography (EUV) potentially being used in pilot production in a few years, it raises the question of larger photomasks sizes—will the industry need them, and if so, when? While there has been discussion of late about the possible need to transition to a larger mask size, veterans of the mask business may feel it's déjà vu all over again. Back... » read more

450mm: Out Of Sync
By Mark LaPedus - 18 Jul, 2013 - Comments: 0

By Mark LaPedus The IC industry has been talking about it for ages, but vendors are finally coming to terms with a monumental shift in the business. The vast changes involve a pending and critical juncture, where the 450mm wafer size transition, new device architectures and other technologies will likely converge at or near the same time. In one possible scenario, 450mm fabs are projected ... » read more

MEMS Foundries Play Waiting Game
By Mark LaPedus - 18 Jul, 2013 - Comments: 0

By Mark LaPedus For years, the foundries in the microelectromechanical systems (MEMS) business have been patiently waiting for the MEMS integrated device manufacturers (IDMs) to outsource some or all of their production. The MEMS foundries are still waiting for that development. Because MEMS are custom devices tuned to a proprietary process and toolset, IDMs still prefer to use their own f... » read more

Trading Off Power And Performance
By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler There is no shortage of opinions when it comes to the topic of performance and power tradeoffs. From abstracting the task from engineers to process considerations, engineering teams have a number of tools and approaches at their disposal to make the optimal design choices for their application. Take the MCU application space for instance. Ken Dwyer, director of app... » read more

Software Debug Gets Tricky
By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler As designs continue to grow in size and complexity, that complexity has led to an increasing number of processing cores. Additional cores, in turn, allow for additional software to be run on those cores, and debugging the software becomes critical. Traditionally, emulation has played a significant role in verifying that software against RTL code, and continues to d... » read more

Dealing With New Bottlenecks
By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling While the number of options for improving efficiency and performance in designs continues to increase, the number of challenges in getting chips at advanced process nodes out the door is increasing, too. Thinner wires, routing congestion, more power domains, IP integration and lithography issues are conspiring to make design much more difficult than in the past. So why aren�... » read more

The Controversial Spec
By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler Design sophistication and complexity has made it increasingly difficult to fully specify the expected behavior of a block in an SoC, but this is necessary for design and verification teams. How do you write a “good” and “complete” specification of functionality? It turns out that the discussion of defining what a good and complete specification is and how t... » read more

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