category: Top Stories

category: Auto, Security & Edge AI

Dealing With The Data Glut
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Tools like emulation and simulation are an absolute necessity to design and verify today’s complex SoCs, but what happens when you want to do power analysis and the file sizes are too massive for the emulator to handle? Even with an emulator a five-minute mobile phone call could take three months. Understandably, this issue is causing pain to many design teams... » read more

x86 Processor Road Map No Longer Just About Speed
By Ed Sperling - 01 Apr, 2013 - Comments: 0

By Ed Sperling The decades-old approach of powerful processors with ever-faster clock speeds is changing. Performance matters in some settings, but the real concern is adding more functionality within power budgets. The most pressing tradeoff is now performance vs. power, which has forced processor architects at AMD, Intel and IBM to take into account everything from application software to... » read more

Experts At The Table: Verification Strategies
By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. What follows are e... » read more

Diverging Viewpoints
By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling The raw materials of semiconductor design include smart, well-trained people and money to fund good ideas from those people, whose backgrounds typically come from engineering, math, physics, computer science, materials science and sometimes even chemistry. While many experts, executives, and industry groups have been sounding the alarm in recent years about everything from la... » read more

Executive Briefing: Wally Rhines
By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling System-Level Design, as part of its ongoing executive briefing series, sat down with Wally Rhines, Mentor Graphics' chairman and CEO, to talk about future problems, opportunities, and the gray areas that could go either way. What follows are excerpts of that conversation. SLD: Is the amount of time spent on verification increasing? Rhines: It depends on how you define who s... » read more

The Evolving Interconnect
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Chip interconnect protocol requirements are evolving as designs move to 20nm and below process geometries, and not always in predictable ways. At least part of this is being driven by what an SoC is used for. The continued push to shrink features opens up real estate at each new process node. For the past decade, that real estate has been used to add more featu... » read more

The Smartphonification Of Things
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler The term, ‘Internet of Things,’ was first coined more than a decade ago by technology visionary Kevin Ashton but has slowly trickled down to the world of chip design and is now mentioned constantly in conversation. The reason is simple: System-level design tools are getting sophisticated enough to handle the intricacies required by devices in an Internet of ... » read more

More Than Data Management
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Managing the people, the data and the technology are just as important as meeting the market window given that without these, the entire project wouldn’t function. Throw huge data set sizes, different cultures and business management issues into the mix and the challenges are many. Fortunately, these are issues that the semiconductor industry has been refining for ... » read more

Continuous, Connected And Concurrent Verification
By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling It’s a wonder that any electronic system works as intended, or that it continues to work months or years after it is sold. The reason: SoCs have become so complex that no verification coverage model is sufficient anymore, no methodology covers every aspect of verification, and no single tool or even collection of tools can catch every bug or prevent them from being there in th... » read more

Wanted: New Metrology Funding Models
By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus The shift toward the 20nm node and beyond will require new and major breakthroughs in chip manufacturing. Most of the attention centers around lithography, gate stacks, interconnects, strain engineering and design-for-manufacturing (DFM). Lost in the conversation are two other critical but overlooked pieces in the manufacturing puzzle—wafer inspection and metrology. ... » read more

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