category: Top Stories

category: Auto, Security & Edge AI

Reaching For The Reset Button In Lithography
By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus Amid ongoing delays and setbacks, extreme ultraviolet (EUV) lithography and multi-beam e-beam have both missed the 10nm logic node. So for the present, chipmakers must take the brute force route at 10nm by using 193nm immersion with multiple patterning. Now, it’s time to hit the reset button. For the 7nm node, chipmakers currently are lining up the lithographic competition... » read more

Making An Impression with Nanoimprint
By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss the trends in lithography with Mark Melliar-Smith, president and chief executive of Molecular Imprints Inc. (MII), a supplier of nanoimprint lithography tools. SMD: How do you view the IC industry now? Melliar-Smith: It’s truly incredible work that this industry continues to do. The industry will see its way f... » read more

Directed Self-Assembly Grows Up
By Mark LaPedus - 21 Mar, 2013 - Comments: 1

By Mark LaPedus At last year’s SPIE Advanced Lithography conference, Christopher Bencher, a member of the technical staff at Applied Materials, said the buzz surrounding directed self-assembly (DSA) technology resembled the fervor generated at the famous Woodstock rock concert in 1969. This was clearly evident from the tumultuous and free-flowing movement that threatened the status quo o... » read more

Verifying Your Intent
By Ann Mutschler - 21 Mar, 2013 - Comments: 0

Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before manufacturing. Checking electrical characteristics of a design is one thing. Verifying power intent is quite another. And the overlap of the two is an intriguing concept. Case in point: Checking fo... » read more

Swimming In Data
By Ed Sperling - 21 Mar, 2013 - Comments: 0

By Ed Sperling So many warnings about data overload have been issued over the past decade that people generally have stopped paying attention to them. The numbers are so astronomical that increases tend to lose meaning. Nowhere is this more evident than in the semiconductor metrology world, where files are measured in gigabytes. And at each new process node, as the number of transistors a... » read more

A Balancing Act
By Ann Mutschler - 14 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler If you stay current on data center trends, you are well-versed on the fact that Intel reported last June energy proportionality has effectively doubled server efficiency and workload scaling beyond what Moore’s Law predicted. What does this have to do with power management of SoCs? Cary Chin, director of marketing for low-power solutions at Synopsys, said tha... » read more

Sprint To The Finish Line
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss future challenges, pain points, and how the supply chain is being reconfigured with Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. What follows are excerpts of that conversation. LPHP: How important is it to be at the front end of Moore’s Law? Hsu: Strategically, it’... » read more

Moore’s Law 2.0
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Doubling the number of transistors on a piece of silicon every 18 to 24 months used to be synonymous with engineering progress, but as the semiconductor world migrates from processors to SoCs the fundamental basis of Moore’s Law is losing its meaning. Even its famous timetable is slipping. For one thing, it’s simply too expensive and difficult to migrate from one node to ... » read more

Version Control
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling & Ann Steffora Mutschler One of the biggest impediments to progress in semiconductor design is progress itself—version after version of specifications, formats and increasingly IP. In fact, there are so many different versions, some of which conflict directly with each other, that it may take months or even years before some customers adopt new products. Much has ... » read more

Hot Stuff
By Ann Mutschler - 14 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to thermal modeling, which has been practiced for many years, the challenges are daunting. The good news is that approaches are emerging as challenges increased with smaller process nodes and design complexity. Viewed from a number of viewpoints—transistor, chip, package, board and system—thermal models traditionally have been created from m... » read more

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