category: Top Stories

category: Auto, Security & Edge AI

Smarter Things
By Ed Sperling - 28 Feb, 2013 - Comments: 0

By Ed Sperling SoC design has largely been a race to the next process node in accordance with Moore’s Law, but it’s about to take a sharp turn away from that as the Internet of Things becomes more ubiquitous. There has been much made about the Internet of Things over the past couple of years—home networks that involve smart refrigerators sending reminders to consumers that the milk is... » read more

Mythbusting: Co-Design
By Ed Sperling - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler It turns out that while there needs to be understanding between hardware and software engineers, the people doing the programming don’t actually want or need to interact. There is not, nor probably ever will be, one single team with hardware and software engineers happily working together on a project. But it’s not a total disconnect. There are a number o... » read more

The New Platform-Based Design
By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Driven by the continued explosion in design costs, the term ‘platform-based design’ is evolving. A platform used to be viewed as an actual chip with some configurability on it that a semiconductor company promoted. Their customers would buy that chip in volume, configure it to their requirements, and sell it inside their end devices. The definition has beco... » read more

The Rise Of Layout-Dependent Effects
By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Designing for today’s advanced semiconductor manufacturing process nodes brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Layout-dependent effects (LDE), which emerged at 40nm and are having a larger impact at 28 and 20nm, introduce variability to circuit ... » read more

Surprises Abound As Subsystem IP Gains Prominence
By The SE Staff - 28 Feb, 2013 - Comments: 0

What’s new in the world of subsystem intellectual property? To find out, System-Level Design sat down with Richard Wawrzyniak, senior market analyst for ASICs and SoCs at Semico Research Corp. What follow are excerpts of that conversation. SLD: You mentioned that the cost of semiconductor intellectual property (IP) at 20nm and below is increasing. Why is that? Wawrzyniak: The reason is c... » read more

Good Pattern Flow Ahead For 14, 10nm
By Ann Mutschler - 21 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node. “They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant... » read more

Getting Ready For High-Mobility FinFETs
By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node. Intel hopes to ramp up its second-generation finFET devices at 14nm by year’s end, with plans to debut its 11nm technology by 2015. Hoping to close the gap with Intel, silicon foundries are accelerating their efforts t... » read more

Foundry Arms Race Under Way
By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus A year ago, chipmakers were reeling from a severe shortage of 28nm foundry capacity, prompting foundries to ramp up their fabs at a staggering pace. At the time, foundries were unable to keep up with huge and unforeseen demand for mobile chips. The shortfall was also caused by low yields and the overall lack of installed 28nm capacity. Today, the 28nm crunch is largely ov... » read more

Optical Lithography, Take Two
By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus It’s the worst-kept secret in the industry. Extreme ultraviolet (EUV) lithography has missed the initial stages of the 10nm logic and 1xnm NAND flash nodes. Chipmakers hope to insert EUV by the latter stages of 10nm or by 7nm, but vendors are not counting on EUV in the near term and are preparing their back-up plans. Barring a breakthrough with EUV or other technology, IC ... » read more

Multicore Madness
By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus Smartphones and tablets are migrating towards new and faster application processors, basebands, graphics chips and memories. In the cell-phone chipset area alone, there are a multitude of options and design considerations. Some devices combine the application processor and modem on the same chip. Some are separate devices. In addition, the architectures range from single- to... » read more

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