category: Top Stories

category: Auto, Security & Edge AI

Routing Congestion Returns
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Routing congestion has returned with a vengeance to SoC design, fueled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. This is certainly not a foreign concept for IC design. The markets for place and route tools were driven largely by the need to automate this kind of operat... » read more

SoC Platforms Gain Steam
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Platforms are attracting far more attention from makers of SoCs because they are pre-verified and can speed time to market, but the shift isn’t so simple. It will spark major changes in the way companies design and build chips, causing significant disruption across the entire SoC ecosystem. Platforms are nothing new in the processor and software world. Intel, IBM AMD, and N... » read more

Wreaking Havoc
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler With PCB circuits running at very fast speeds today, the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance comes with specific physical layout requirements that are not obvious. There are unexpected challenges, important high-speed considerations and efficient ways to account for them in high-spe... » read more

Smarter Co-design With Models
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler IC, package and PCB co-design methodologies are starting to be adopted by semiconductor companies. However, the existing die abstract file used in these flows to exchange data between the IC designer and the downstream package design team may not contain enough detail to drive advanced planning and optimization with the package and PCB interfaces. Engineering teams... » read more

More Design Rules Ahead
By Ed Sperling - 25 Jul, 2012 - Comments: 0

By Ed Sperling & Mark LaPedus For those companies that continue to push the limits of feature shrinkage, designs are about to become more difficult, far more expensive—and much more regulated. Two converging factors will force these changes. First, the limits of current 193nm immersion lithography mean companies now must double pattern at 20nm, and potentially quadruple pattern at 14n... » read more

Bridging The Rift Between Software And Hardware
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling As more computing is done on mobile devices rather than desktops, the idea of what constitutes good application software is changing. This addresses the key reason why some of advanced power-saving features built into chips were not utilized by software in the past. Unless the operating systems were specifically written for mobile devices, such as Android and iOS, the real f... » read more

28, 20nm Nodes Demand Advanced Power Management
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler With the complexity of getting 28 and 20nm designs to reach desired yields with the desired power and performance on the shoulders of design teams, advanced power management techniques are a must. Sub-clock power gating, clock power gate structures, adaptive body bias and other techniques are making it possible. Sub-Clock Power Gating Far from a new techniqu... » read more

Four Factors Driving Processor Choices
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Choosing processors for an SoC, a system-in-package, or even a complete system is becoming much more difficult, and the challenge is growing as demands on performance, power, area and time to market continue to increase. There are many reasons why this is becoming more difficult—and some designs will require more tradeoffs than others, depending upon IP re-use or a particul... » read more

Testing the Waters
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler Large semiconductor companies are now testing the waters in 3D design to determine how to best leverage the technology for lower power, better performance and additional architectural flexibility. As such, much work is being done to determine how exactly to achieve an optimum 3D design outcome. 3D is almost by definition an architectural approach to power sav... » read more

Architectural Changes Will Drive Miraculous 3D Gains
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler Low-Power High-Performance Engineering sat down with Robert Patti, chief technology officer at Tezzaron Semiconductor, to discuss future challenges with regard to 2.5D and 3D design, including making tradeoffs and technical issues specific to 3D design. Tezzaron currently is working on 3D designs. LPHP: What is the starting point technically to achieve the gre... » read more

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