category: Top Stories

category: Auto, Security & Edge AI

Analog Hits The Power Wall
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ed Sperling Analog design teams are starting to encounter the same physical issues that digital design engineers began wrestling with several nodes ago—only the problems are more complicated and even more difficult to solve. At advanced nodes digital circuitry is susceptible to an array of physical effects ranging from heat, electromigration, electromagnetic interference and electrosta... » read more

Mining For Data
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler Power analysis accuracy at the RTL design abstraction is a challenging problem. Smaller geometries just make the challenge of predicting accurate RTL power consumption even more difficult, which in turn impacts other design decisions such as power-grid planning and package selection. “It’s one of these things where the earlier you are in the design, even befo... » read more

The New Frontier: Low-Power Verification And Test
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler By now there’s no argument that verification and test strategies must be considered at the very earliest stages of any design cycle, and when it comes to low-power designs, the advanced techniques used and design complexity make the challenges here even more daunting. Low-power verification and test strategies have been in development for a number of years, and it... » read more

The Rise Of The Power Architect
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler Call them power czars, power gurus or power architects, this role within design teams is gaining importance with the need to understand, manage and control the power budget throughout the entire design process. As such, power architects are in high demand today with power architecture teams doubling in size within a year or two. Driving the need for this highly s... » read more

The Easy Stuff Is Over
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ed Sperling Doomsayers have been predicting the end of Moore’s Law for the better part of a decade. While it appears that it will still remain viable for some companies—Intel and IBM already are looking into single digits of nanometers and researchers speculating about picometer designs—for most companies the race is over. Progress will still be made in moving SoCs from one node to... » read more

Capping Tools Tame Electromigration
By Mark LaPedus - 31 Jul, 2012 - Comments: 0

By Mark LaPedus The shift towards the 28nm node and beyond has put the spotlight back on the interconnect in semiconductor manufacturing. In chip scaling, the big problem in the interconnect is resistance-capacitance (RC). Another, and sometimes forgotten, issue is electromigration. “Electromigration gets worse in device scaling,” said Daniel Edelstein, an IBM Fellow and manager of BE... » read more

EUV Remains Elusive
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By David Lammers Intel’s decision to invest as much as $4.1 billion in ASML has raised overall confidence levels in EUV lithography, and should allow the Dutch lithography vendor to funnel more funds into the stubbornly difficult effort to raise the EUV source power. ASML has said it needs to reach 250 Watts of average source power to achieve the 125 wph throughputs sought by its early cu... » read more

Firms Rethink Fabless-Foundry Model
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Mark LaPedus As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model. Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the found... » read more

The Changing Role Of The OSAT
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler As process geometries and packaging technologies have matured over time, the OSAT (outsourced semiconductor assembly and test) provider has played an evolving role in the semiconductor packaging ecosystem. With true 3D chip stacking on the horizon, their role may evolve once again as ecosystem players jostle for position in the 3D universe. There are two things tha... » read more

DSA Moves To R&D Pilot Lines
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Mark LaPedus Directed self-assembly (DSA), an alternative lithography technology that makes use of block copolymers, is still in the R&D stage for semiconductor production. But as the exotic patterning technology continues to make astounding progress, there are signs the IC industry is accelerating its efforts to bring DSA from the lab to the fab. In fact, DSA suddenly has become a ... » read more

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