category: Top Stories

category: Auto, Security & Edge AI

Blurring The Lines At The OS Level
By Ed Sperling - 13 Sep, 2012 - Comments: 0

By Ed Sperling Picking an operating system—or choosing not to use an operating system—is becoming as complex a decision as choosing which IP to use in an SoC. Even decisions that sound straightforward may have ramifications on the total system power budget or performance, requiring them to be an integral part of the overall architectural process. But the choice of operating systems, as ... » read more

Inflection Points Ahead
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Engineering challenges have existed at every process node in semiconductor designs, but at 20nm and beyond, engineers and executives on all sides of the industry are talking about inflection points. An inflection point is literally the place where a curve on a graph turns down or up, but in the semiconductor industry it’s usually associated with the point at which a progres... » read more

Dealing With Test More Effectively
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Shrinking geometries are starting to have the same effect on test as they are on other parts of an SoC, with the focus shifting from area to leakage, heat, noise, signal integrity, and the impact on overall system performance. The warning that design teams have to consider test much earlier in the design was issued to chipmakers years ago and largely ignored. At 28nm that war... » read more

Best Practices In Verification
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler The advent of advanced verification methodologies such as the UVM and its predecessors VMM and OVM has changed the verification landscape in many ways. Design and verification teams used to worry about simulator performance (i.e., how fast the simulator runs a particular test case), but the introduction of constrained-random stimulus and functional coverage and associ... » read more

Being Different Is Bad
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler Today’s SoCs contain as much as 80% existing IP that either has been re-used from previous projects or obtained from a third party. Models are created of this hardware IP, as well as new portions of the design, in order to create a virtual prototype that allows the engineering team to see the complete system by running software and applications. While this a... » read more

What Comes After FinFETs?
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By Mark LaPedus The semiconductor industry is currently making a major transition from conventional planar transistors to finFETs starting at 22nm. The question is what’s next? In the lab, IBM, Intel and others have demonstrated the ability to scale finFETs down to 5nm or so. If or when finFETs runs out of steam, there are no less than 18 different next-generation candidates that could o... » read more

G450C To Align Vendors During 450mm Transition
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By David Lammers Innovation and synchronization among multiple companies do not often go hand in hand. But for the 450mm wafer transition to provide its full benefits, chip makers and their suppliers will need to do more than a simple wafer size scale up. That may lead the Global 450 Consortium (G450C) to serve as the proving ground for efforts to more closely match the electrical results o... » read more

3D-IC Impact On Computational Lithography?
By Ann Mutschler - 16 Aug, 2012 - Comments: 0

While 3D devices and technology such as through-silicon vias (TSVs) definitely complicate matters in the design, verification and manufacturing space, one might assume there would also be an impact on the computational lithography tools that are used to ensure printability. Have no fear. Industry experts assure us that this is not the case. Lithography expert Chris Mack acknowledged that ... » read more

LED Firms Mull New Wafer Sizes And Materials
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By Mark LaPedus Seeking to reduce the cost of solid-state lighting and related applications, LED manufacturers are taking a page from the IC industry: They are looking at larger wafer sizes and new materials in the fab. Today, the state-of-the-art LED fab is a 150mm (6-inch) facility, but a large percentage of these plants are still using 50mm (2-inch) substrates. The vast majority of LED s... » read more

What’s After NAND Flash?
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By Mark LaPedus For years, many have predicted the end of flash memory scaling, particularly NAND, but the technology continues to defy the odds as it moves down the process curve. Still, there are signs that the floating gate structure in today’s flash memory is on its last legs. The floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio. And ... » read more

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