What Is SOTIF?


Arteris IP’s Kurt Shuler discusses new system-level best-practices approach to automotive design that will be used for both diagnostics and forensics when something goes wrong with autonomous vehicles. https://youtu.be/nC3TkF7c0Oo » read more

Using ASICs For AI Inferencing


Flex Logix’s Cheng Wang looks at why ASICs are the best way to improve performance and optimize power and area for inferencing, and how to add flexibility into those designs to deal with constantly changing algorithms and data sets. https://youtu.be/XMHr7sz9JWQ » read more

The Next Big Chip Companies


Rambus’ Mike Noonen looks at why putting everything on a single die no longer works, what comes after Moore’s Law, and what the new business model looks like for chipmakers. https://youtu.be/X6Kca8Vm-wA » read more

eFPGA vs. FPGA Design Methodologies


Namit Varma, senior director of Achronix’s India Technology Center, discusses the differences between discrete and embedded FPGAs. https://youtu.be/Vwo3ktQvcKc » read more

802.11ax: Faster Wireless


Marvell's Sathya Subramanian talks with Semiconductor Engineering about the new 802.11ax wireless standard, how it will work with 5G and existing networks, and how to set up an integrated solution to reduce bottlenecks in the home and in the enterprise. https://youtu.be/KZP59qw6j4Y » read more

AI, ML Chip Choices


Flex Logix’s Cheng Wang talks about which types of chips work best for neural networks, AI and machine learning. https://youtu.be/k7OdP7B10o8 » read more

Embedded FPGA Timing


Namit Varma, senior director of Achronix’s India Technology Center, explains how to time an eFPGA, what can go wrong, what are the different clocking scenarios, and what impact variation has on the process. https://youtu.be/Jq4XUKnniB4 » read more

7nm Design Challenges


Ty Garibay, CTO at ArterisIP, talks about the challenges of moving to 7nm, who’s likely to head there, how long it will take to develop chips at that node, and why it will be so expensive. This also raises questions about whether chips will begin to disaggregate at 7nm and 5nm. https://youtu.be/ZqCAbH678GE » read more

Embedded FPGA Design Considerations


Geoff Tate, CEO of Flex Logix, talks about interconnects, memory, different design approaches, and why foundry processes are critical to eFPGA design. https://youtu.be/FngrgDnJn9c » read more

Tech Talk: ISO 26262 Drilldown


ArterisIP’s Kurt Shuler looks at what can go wrong in automotive design, what are the prerequisites for getting the attention of Tier 1 and OEMs, and what’s involved in automotive design at all levels. https://youtu.be/nnjAldn-nKU » read more

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