Nanosheet FET library; fab equipment sustainability; 2D contract resistance; hybrid memory compression; ECRAM for analog NN; data filtering within NAND flash chip; cryogenic FETs.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node | Samsung Electronics and Kyungpook National University (KNU) |
| Search-in-Memory (SiM): Reliable, Versatile, and Efficient Data Matching in SSD’s NAND Flash Memory Chip for Data Indexing Acceleration | TU Dortmund, Academia Sinica, and National Taiwan University |
| Achieving Sustainability in the Semiconductor Industry: The Impact of Simulation and AI | Lam Research |
| HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory | Chalmers University of Technology and ZeroPoint Technologies |
| Retention-aware zero-shifting technique for Tiki-Taka algorithm-based analog deep learning accelerator | Pohang University of Science and Technology, Korea University, and Kyungpook National University |
| Improvement of Contact Resistance and 3D Integration of 2D Material Field-Effect Transistors Using Semi-Metallic PtSe2 Contacts | Yonsei University, Korea Advanced Institute of Science and Technology (KAIST), Lincoln University College, Korea Institute of Science and Technology (KIST), and Ewha Womans University |
| Ultra-steep slope cryogenic FETs based on bilayer graphene | RWTH Aachen University, Forschungszentrum Julich, National Institute for Materials Science (Japan), and AMO GmbH |
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