Better performance, power by eliminating load instructions; CXL survey; chip placement with diffusion; HW architecture, device placement; RTL verification for secure spec; battery electronification; nanoscale trilayer for ultrafast charge transfer; CHERI RISC-V.
New technical papers recently added to Semiconductor Engineering’s library, including a best paper award winner at ISCA.
| Technical Paper | Research Organizations |
|---|---|
| An Introduction to the Compute Express Link (CXL) Interconnect |
Intel Corporation, Microsoft, and University of Washington |
| Integrated Hardware Architecture and Device Placement Search | Georgia Institute of Technology and Microsoft Research |
| Chip Placement with Diffusion | UC Berkeley |
| Mon CHÈRI <3 Adapting Capability Hardware Enhanced RISC with Conditional Capabilities |
Ericsson Security Research, Université Libre de Bruxelles, and KU Leuven |
| RTL Verification for Secure Speculation Using Contract Shadow Logic | Princeton University, MIT CSAIL, and EPFL |
| Constable: Improving Performance and Power Efficiency by Load Instruction Execution |
ETH Zürich and Intel Corporation *Best Paper At ISCA* |
| Battery electronification: intracell actuation and thermal management | Pennsylvania State University and EC Power |
| Ultrafast Charge Transfer Cascade in a Mixed-Dimensionality Nanoscale Trilayer | National Renewable Energy Laboratory |
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