CXL-based memory pooling; carbon nanotube wiring; model checking; side-channel attacks via NVM; compiler for HDL; energy-efficient mapping of NN; equivalence checking; flip chip bonding; LIM operation of ternary NAND/NOR universal logic gates; sizing analog transistors.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Pond: CXL-Based Memory Pooling Systems for Cloud Platforms | Virginia Tech, Intel, Microsoft Azure, Google, and Stone Co. |
| Direct formation of carbon nanotube wiring with controlled electrical resistance on plastic films | Tokyo University of Science |
| Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking | ETH Zurich |
| NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems | UC San Diego, UT Austin, and Purdue University |
| A Multi-threaded Fast Hardware Compiler for HDL | UC Santa Cruz |
| Energy-Efficient Mapping of Dynamic Neural Nets onto Heterogeneous MPSoCs | LAMIH/UMR CNRS, Universite Polytechnique Hauts-de-France and UC Irvine |
| An Equivalence Checking Framework for Agile Hardware Design | Portland State University and Intel |
| Flip chip bonding on stretchable printed substrates; the effects of stretchable material and chip encapsulation | Silicon Austria Labs and Institute for Smart Systems Technologies |
| Logic-in-Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double-Gated Feedback Field-Effect Transistors | Korea University |
| APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning | UT Austin and Analog Devices |
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