Chip Industry’s Technical Paper Roundup: Oct 25
Core & cache hierarchy for M3D; In-DRAM PIM; RF transceivers piracy; semiconductor defects; nonvolatile electrochemical RAM under short circuit; electrotactile system; optical interconnects; graphene transfers
New technical papers added to Semiconductor Engineering’s library this week.
| Technical Paper |
Research Organizations |
| RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory |
ETH Zürich, KMUTNB, NTUA, and University of Toronto |
| Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling |
Korea University |
| Nonvolatile Electrochemical Random-Access Memory Under Short Circuit |
University of Michigan and Sandia National Laboratories |
| Anti-Piracy Design of RF Transceivers |
Sorbonne Universite (France) |
| Polycrystalline silicon PhC cavities for CMOS on-chip integration |
Tyndall National Institute, Munster Technological University, and Université Grenoble Alpes, CEA, LETI |
| Assessment of wafer-level transfer techniques of graphene with respect to semiconductor industry requirements |
RWTH Aachen University, AMO GmbH, Infineon Technologies, Protemics GmbH, and Advantest Europe |
| Simulating groundstate and dynamical quantum phase transitions on a superconducting quantum computer |
London Centre for Nanotechnology, University College London, University of Massachusetts, and Google Quantum AI |
| Super-resolution wearable electrotactile rendering system |
City University of Hong Kong & Tencent Technology’s Robotics X Laboratory |
| Exploring Active Learning for Semiconductor Defect Segmentation |
Agency for Science, Technology and Research (A*STAR) in Singapore |
|
|
|
|
Linda Christensen
(all posts)
Linda Christensen is vice president of operations and a contributing writer at Semiconductor Engineering.
Leave a Reply