Demand for AI chips is growing exponentially, but costs and complexity limit the technology to a handful of companies. That could soon change.
The rapidly increasing demand for advanced-node chips to support everything-AI is putting pressure on the industry’s ability to meet demand.
The need for cutting-edge semiconductors is accelerating in applications ranging from hyperscale data centers powering large language models to edge AI in smartphones, IoT devices, and autonomous systems. But manufacturing those chips relies heavily on extreme ultraviolet (EUV) lithography, which has become one of the biggest barriers to scaling production. Since the first commercial EUV chips rolled off the line in 2019, steady improvements in equipment, mask generation, and resist technologies have stabilized the technology. But while yields are improving, they still lag behind more mature lithography techniques.
Process stability requires constant vigilance and fine-tuning. In the case of EUV, it also requires a huge investment for power generation, equipment, and consumables. Today, those costs remain a barrier to widespread adoption. But the industry is not standing still. Intensive research and development efforts are underway, targeting everything from novel resist materials and more robust light sources to advanced mask writers and sophisticated AI-driven process control.
“Fab productivity depends on multiple factors — throughput, process efficiency, and accurate pattern transfer,” said Dinesh Bettadapur, CEO of Irresistible Materials. “Reducing exposure dose, improving resist sensitivity, and minimizing defects are all critical factors in making EUV more cost-effective at scale.”
AI demand curve turns vertical
The increasing demand for advanced-node semiconductors is reshaping the industry. AI workloads, high-bandwidth memory (HBM), and the next generation of mobile and computing devices are all driving a shift toward finer process nodes. Each iteration requires more sophisticated fabrication techniques using EUV, with high-NA EUV emerging as the only viable path forward for high-volume production at 1.8nm and below.
AI accelerators, large-scale GPUs, and high-performance CPUs require ever-smaller transistors to maximize power efficiency and computational density. Leading-edge AI chips from Nvidia, AMD, and Intel already depend on EUV-fabricated 5nm and 3nm process nodes, and the shift toward 2nm gate-all-around (GAA) transistors will further increase demand for EUV’s capabilities.
The same is true for some aspects of HBM production, where Samsung, Micron, and SK hynix are deploying EUV selectively, primarily for logic and peripheral circuits rather than the memory cell array itself. While EUV helps increase density and improve patterning precision in HBM stacks, deep ultraviolet (DUV) lithography remains dominant for core memory layers. As AI workloads scale, however, the need for ultra-high-bandwidth memory will expand to match, making EUV-enabled HBM components increasingly critical.
“If you are going to make devices with very high transistor counts, then you want to do it with the smallest features you can,” said Harry Levinson, principal lithographer at HJL Lithography. “The market for EUV will be the chips with the highest transistor counts. Of course, the standard for what is considered ‘high’ moves over time, but AI accelerators, GPUs, and mobile processors are all pushing those limits today.”
Beyond AI and HBM, next-generation logic devices for 5G, autonomous systems, and edge computing also will require EUV’s resolution advantages for some critical layers. The fundamental challenge is that while demand for AI chips is growing exponentially, the number of fabs capable of producing EUV-based chips remains limited.
Today, only five semiconductor manufacturers operate EUV in high-volume production — TSMC, Samsung, Intel, SK hynix, and Micron. These companies collectively produce all of the 5nm logic and memory devices, concentrating EUV capability within a small number of companies.
Japan’s Rapidus is now emerging as a sixth player in this market. The eight-member consortium — which includes Toyota, Sony, MUFG Bank, NTT, Denso, Kioxia, NEC, and Softbank — installed ASML’s NXE:3800E EUV scanner at its IIM-1 fab in Hokkaido, Japan, with plans to begin high-volume production in 2027.
Still, the opportunity for EUV remains limited. “The real question isn’t whether EUV works — it does,” said Larry Melvin, principal engineer at Synopsys. “The challenge is whether fabs outside the largest players can justify the cost. Every improvement in mask technology, resist chemistry, and scanner efficiency helps, but without fundamental reductions in equipment and operational expenses, EUV will remain limited to a select few.”
The growing demand for advanced-node chips already outpaces EUV production capacity, with ASML struggling to keep up with orders. TSMC’s Arizona fabs, Intel’s U.S. and Ireland expansions, and Samsung’s Texas foundry projects all require more EUV capacity to meet their high-volume manufacturing goals this year and next. Those expansions will further exacerbate the supply-demand gap.
The market for AI chips is forecast to grow to at least 10 times its current size in the next 5 to 7 years.[1,2,3] TSMC already has a backlog on its 2nm process orders that extends through 2026.[4]
The EUV equipment bottleneck
ASML, the sole supplier of EUV scanners, has been racing to keep up with demand, but multi-year backlogs continue to limit the expansion of new EUV production lines. The company’s most advanced tools, such as the NXE:3800E and the upcoming EXE:5000 high-NA system, already are on allocation to leading semiconductor manufacturers for years in advance. And with demand for AI chips, HBM, and advanced mobile processors growing exponentially, existing EUV production lines are under intense pressure to improve throughput, yield, and overall efficiency to compensate for the industry’s constrained ability to scale.
Government-backed research centers are stepping in to help bridge the gap. Facilities like imec in Belgium and the CHIPS Act-funded EUV Accelerator in Albany, New York, are focused on pushing EUV mask technology, process control, and resist chemistry forward to increase yield and drive down per-wafer costs. Imec has played a central role in testing and validating next-generation mask materials that can enhance feature resolution while reducing stochastic defects.
The EUV Accelerator, backed by an $825 million federal investment, is taking a similar approach in the United States, providing access to cutting-edge EUV tools and research platforms to accelerate manufacturability and industry adoption. These efforts, combined with private-sector R&D, are targeting the key technological hurdles that continue to make EUV an expensive and complex process.
With access and cost limiting EUV access, many fabs operating just below the leading edge are turning to creative lithography strategies to remain competitive. Hybrid lithography — where EUV is used only for the most critical layers, while 193nm ArF, ArF immersion, and KrF (248nm) scanners handle less demanding features — has become the standard. Multiple patterning techniques, such as double and quadruple patterning, have extended the reach of DUV well beyond its initial capabilities, allowing fabs to produce smaller feature sizes without having to make EUV investments. Additionally, some companies are exploring nanoimprint lithography (NIL) and self-assembled patterning for specific layers where these techniques can provide cost or resolution advantages.
“Despite the strong adoption of EUV lithography for the critical layers of advanced nodes, 248nm and 193nm lithographies continue to be widely used, even at the leading-edge, for non-critical logic layers, NAND flash, as well as some tight-pitch layers through multiple patterning,” said Levinson. “Innovations in process control and mask technology have allowed DUV to remain a viable option for many layers, offering fabs a cost-effective way to extend existing tools rather than transitioning everything to EUV.”
Looking forward, EUV and high-NA EUV undoubtedly will drive advanced-node semiconductor manufacturing, but alternative lithography approaches will continue to play a critical role even if EUV technology reaches a cost and technology improvement threshold that justifies broader industry adoption.
One of the most persistent technical challenges in EUV lithography is the mask infrastructure. Unlike traditional deep ultraviolet (DUV) lithography, which uses transmissive masks, EUV masks are reflective, a fundamental shift that introduces a host of new failure modes. Even microscopic defects can distort reflected light and lead to catastrophic patterning failures, driving up defect rates and reducing yield.
To mitigate these issues, researchers are refining multi-beam mask writers, high-transparency pellicles, and pushing toward defect-free mask blanks. Multi-beam electron-beam mask writing technology already is making a significant impact by reducing the time required to create highly precise, defect-free masks. Traditional single-beam mask writers are slow and prone to patterning errors, but multi-beam systems use thousands of parallel electron beams to accelerate production while maintaining sub-nanometer precision.
Pellicle technology, the protective layer over masks, also has seen substantial improvements. Early EUV pellicles were highly fragile and suffered from low transmission efficiency, reducing scanner productivity. New carbon-based pellicles dramatically improve both thermal stability and transmission rates, extending the life of masks without degradation. That, in turn, reduces the need for frequent mask replacements, which is an expensive and time-consuming process. In addition, it improves wafer-to-wafer consistency.
“Most of the cost – about $100,000 per mask blank – is driven by yield,” said Levinson. “Yields have been improving, but prices remain high because blank makers are investing heavily in additional manufacturing capacity to meet customer demand. At some point, that will saturate with the current customer base. But for now, cost remains high.”
These advances in mask durability, pattern fidelity, and overall defect control help fabs push EUV yields closer to parity with more established DUV techniques, but mask costs remain a significant financial burden. The industry is actively working to address these economic challenges alongside the technical ones.
Material advancements
Photoresist materials remain a critical challenge in achieving high yields and process stability for EUV lithography. Chemically amplified resists (CARs) have been the industry standard for decades, but acid diffusion and stochastic defects at advanced nodes limit their ability to meet the stringent requirements of next-generation semiconductor manufacturing.
“We are at a point where it’s going to be very hard to improve resist materials because the size of resist molecules is now an appreciable fraction of the feature size,” said Harry Levinson, an independent lithography expert. “You can’t just swap one chemical for another. Addressing this challenge also will require more photons per square centimeter to combat photon shot noise, which is a fundamental physics constraint.”
As feature sizes shrink further, new approaches are required to improve resolution, reduce line-edge roughness (LER), and increase sensitivity while maintaining process stability. But the tradeoffs between these factors present a persistent engineering challenge.
“Delivering resolution, line-edge roughness, and sensitivity all at once is a real challenge,” said Rich Wise, vice president at Lam Research. “You often see results that focus on two, neglecting the third, and that can slow down scanner productivity.”
To overcome the limitations of CARs, the industry is exploring several alternative resist platforms. One option is metal-oxide resists (MORs), which offer strong absorption at EUV wavelengths and improved contrast at lower thicknesses. However, traditional MORs can be highly sensitive to process conditions and require higher doses, creating yield and throughput challenges.
Lam introduced its Aether dry resist technology, which applies MORs using vapor-phase deposition instead of spin-coating. This enhances process control, reduces stochastic variability, and improves photon absorption efficiency, ultimately lowering dose requirements and improving patterning resolution at finer pitches.
“While progress in EUV scanner power, reliability, and numerical aperture has been promising, photoresists have become a limiting factor in advancing direct print EUV,” said Wise, in a presentation at Semicon Korea. “Current spin-coated photoresists struggle to meet the stringent sensitivity, resolution, and defectivity demands required for high-volume manufacturing (HVM) at advanced technology nodes.”
Another approach is the multi-trigger resist (MTR) platform, developed by Irresistible Materials. MTR uses a molecule roughly 10 times smaller than existing polymers, allowing for smaller feature sizes and improved resolution. Unlike CARs, MTR employs a controlled catalytic process that minimizes acid diffusion while maintaining high photon absorption and sensitivity.
“The requirements for EUV are so demanding that no single resist formulation or process fully meets the diverse set of needs across different device types and layers,” said Bettadapur. “Process compatibility, delay tolerance, and line width roughness remain areas where improvements are continually needed.”
Both MORs and MTRs offer advantages, but they also have unique process sensitivities that fabs must address.
“Photoresist types have different challenges,” said Douglas Guerrero, senior technologist at Brewer Science. “For chemically amplified resists, decreasing depth of focus (DOF) will require thinner films. As the films become thinner, the contrast will be lower than current resists, while simultaneously increasing roughness. Metal-oxide resist has the advantage of good contrast even at a lower thickness. It shows good resolution capabilities, but sensitivity to the process is a challenge to control.”
Beyond resolution and LER, defectivity remains a critical issue that directly impacts EUV’s viability in high-volume manufacturing. Even minor defects in the resist can result in patterning failures, yield loss, and increased costs.
“Defectivity is an important parameter to optimize and control to ensure process scalability and introduction into device manufacturing,” said Daniel Soden, business development manager at Brewer Science. “Good lithography performance is key, but defectivity needs to be kept low and stable to ensure high process yield and fully realize the benefits of EUV lithography.”
The push for lower defectivity has driven advancements in material purification and filtration techniques, but polymer design and additive functionality are becoming more critical than ever as underlayers shrink from between 25-to-30nm to just 1-to-10nm. Longer term, resist innovation will require a fundamental shift in material science.
“We will need molecular-level control,” said Guerrero. “We are approaching films no more than a few hundred molecules thick, where every atom counts and contributes to the properties of the material. Bulk behavior will no longer have an impact on the overall material property. Molecular design and positioning will need to have angstrom-level precision.”
As semiconductor manufacturers transition to high-NA EUV, these material constraints will become even more pronounced, necessitating novel resists and underlayers that push the boundaries of molecular engineering. While no single resist platform currently meets all EUV requirements, ongoing advancements in CARs, MORs, MTRs, and dry resists represent multiple pathways to solving EUV’s most pressing material challenges.
AI process control
Beyond physical improvements to masks and resists, fabs increasingly rely on AI and machine learning to optimize process control, defect detection, and yield enhancement. Companies like Tignis and Synopsys are at the forefront of integrating AI-driven metrology tools that analyze process variability in real-time and correct for variability that impacts yield.
“Advanced lithography has well over 1,000 equipment and process parameters that need to be characterized and monitored for quality outcomes,” said Boyd Finlay, director of solutions engineering at Tignis. “Our automated one-click style correlation engine has been demonstrated to show multi-layer variables as they affect CD as well as other response factors of interest. These complex data relationships are then incorporated automatically into our low-code language (digital twin query language, or DTQL) algorithms that can be scheduled for AI-based process monitoring and control strategies.”
These AI-driven systems allow fabs to dynamically adjust scanner parameters based on real-time data, optimizing exposure doses, alignment tolerances, and resist bake conditions to reduce variation. Machine learning models trained on thousands of wafers can identify trends in stochastic defects and suggest corrective actions before they lead to costly yield losses.
“This is accelerating EUV development cycles of learning, enabling first-time-right patterning, while delivering rapid on-demand troubleshooting for our customers,” said Finlay. “Our solutions can also optimize multi-step processes, such as litho and etch, expanding the benefits of AI beyond singular processes to improve process issues such as overlay error.”
As EUV adoption scales, AI-driven process control will be a key differentiator between fabs that successfully maximize scanner throughput and those that struggle with persistent variability.
The path to scaling EUV
One of the biggest cost drivers for EUV is the light source. EUV lithography relies on high-energy laser sources to generate extreme ultraviolet light at a wavelength of 13.5 nm. These light sources are notoriously inefficient, with much of the energy lost before it reaches the wafer.
ASML’s latest generation scanners consume several hundred kilowatts per system, translating to immense operational costs. While some power consumption improvements have been achieved, further progress is necessary to make EUV a viable option for second-tier fabs.
“It can take a substation to power an EUV scanner fleet,” said Synopsys’ Melvin. “EUV exposure shots used to require around 100 kW of energy. That has improved, but power efficiency remains a major issue.”
Much of this is due to the fact that EUV scanners contain 6 mirrors. “The more mirrors in the optical path, the more energy is lost,” Melvin said. “Each mirror absorbs roughly 40% of the light that passes through it, so by the time it reaches the wafer only a small fraction of the original energy is left.”
Researchers at Lawrence Livermore National Laboratory (LLNL) are exploring alternative laser-driven plasma sources that could significantly improve EUV power efficiency. Their work aims to reduce the energy required to generate EUV photons, thereby lowering the per-wafer cost while maintaining throughput. Additionally, the high-brightness laser sources could enable more compact and cost-effective EUV tools in the future.
“EUV lithography is already pushing the limits of existing laser-driven plasma sources, and finding ways to improve conversion efficiency and scalability is crucial,” said Brendan Reagan, group leader in the Advanced Photon Technologies Group at LLNL.
Instead of using traditional CO2 lasers to generate the plasma needed for EUV light, LLNL is developing diode-pumped solid-state lasers (DPSSLs), which offer higher electrical efficiency and lower overall power consumption. These lasers operate at a shorter infrared wavelength, improving the absorption rate of the tin droplets that generate EUV light, which in turn increases photon conversion efficiency.
“While CO2-driven EUV sources have served the industry well, they are inherently inefficient, with wall-plug efficiencies in the low single-digit percentages,” Reagan said. “We believe thulium-based systems could be 5 to 10 times more efficient, significantly reducing energy waste while maintaining the necessary power levels for high-volume lithography.”
By optimizing this process, LLNL’s approach could reduce both energy costs and heat dissipation, potentially allowing for more compact and modular EUV systems. In theory, lower-energy pulses from DPSSLs also could lead to less thermal strain on pellicles, extending their usable lifespan and reducing the frequency of mask contamination events. However, the impact on pellicle durability also depends on factors such as peak pulse energy, repetition rate, and heat dissipation dynamics within the scanner. Those areas still require further study.
“Moving from proof-of-concept to an industrial solution requires overcoming several hurdles, including integration into existing EUV source designs, said Jackson Williams, lead for high-intensity laser-driven sources at LLNL. “The semiconductor industry is understandably risk-averse, so any new laser source must integrate seamlessly with existing EUV stepper optics and infrastructure. The ability to use a different laser front-end while keeping much of the existing EUV system unchanged could make this transition more feasible.”
Meanwhile, the Okinawa Institute of Science and Technology (OIST) is taking a different approach, investigating ways to improve photon utilization within the scanner itself. Its research targets optical losses in the reflective mirror system, which currently absorbs a significant portion of the available EUV energy. By optimizing mirror coatings and reducing optical aberrations, researchers hope to increase the percentage of light that reaches the wafer, thereby enhancing tool efficiency and reducing exposure times.
Expanding EUV beyond the leading-edge fabs
For EUV to scale beyond the world’s largest chipmakers, alternative business models and infrastructure strategies will be necessary to overcome the high cost of implementation.
“It’s not just the exposure tools,” said Levinson. “It’s all the other pieces of equipment in the line that you have to invest in, such as those for mask inspection, making it a major financial risk.”
Finally, shared EUV infrastructure at research centers like imec and the CHIPS Act-funded EUV Accelerator could provide a collaborative approach to commercialization. Expanding these efforts beyond R&D and into production partnerships could allow fabless semiconductor companies and smaller foundries to access EUV technology without needing to shoulder the full cost burden of a dedicated EUV line.
“A strategy along the lines of chiplets is needed to make this happen for follow-on adopters of EUV,” said Melvin. “There could be a strong marketplace for fabs specializing in I/O chiplets and memory chiplets that get integrated into multiple end products, rather than every fab trying to justify full-node EUV adoption.”
Each of these models represents a potential solution for broadening EUV adoption, but all depend on continued advancements in cost reduction, process control, and infrastructure development. The demand for EUV-based chips is only accelerating, and whether the technology can scale beyond the industry’s largest players will define the next phase of semiconductor manufacturing.
Conclusion
The road ahead for EUV lithography is defined by a race between rising demand and the industry’s ability to scale. The next generation of advanced-node processors will power AI-driven data centers, autonomous systems, and high-bandwidth computing, pushing fabrication capacity to its limits. Meeting this demand will require more than incremental improvements. It will take fundamental shifts in how EUV is deployed and accessed. Expanding the supply of EUV tools, improving cost efficiency, and developing innovative approaches to mask production and process control will determine how widely the technology can be adopted beyond the industry’s largest players.
To keep pace, the industry must accelerate breakthroughs in resist materials, refine high-yield process controls, and push the boundaries of power-efficient light sources. The push for greater EUV adoption also will require new business and manufacturing models, enabling smaller fabs to integrate advanced lithography into their production pipelines. EUV already has reshaped semiconductor manufacturing. It’s next evolution will determine how the industry expands access to this crucial technology.
References
Related Reading
Key Technologies To Extend EUV To 14 Angstroms
Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.
Single Vs. Multi-Patterning Advancements For EUV
EUV patterning has come a long way in the past five years, but old challenges resurface with high-NA EUV.
 |
 |
 |
 |
 |
 |
 |  |
Hi Gregory. Thank you for sharing your in depth views specific to AI growth thru the lens of euv lithography. I will be giving a talk on AI infrastructure future directions & challenges at next month at Apex2025, and at some point would like to connect with you