Inside Panel-Level Fan-Out Technology

Semiconductor Engineering sat down to discuss panel-level fan-out packaging technology with Tanja Braun, deputy group manager at the Fraunhofer Institute for Reliability and Microintegration IZM, and Michael Töpper, business development manager at Fraunhofer IZM. Braun is responsible for the Panel Level Packaging Consortium at Fraunhofer IZM, as well as the group manager for assembly and encapsulation technologies at the German R&D organization.

Last year, Fraunhofer launched the Panel Level Packaging Consortium. The members of the consortium include Intel, Ajinomoto, ASM Pacific, Atotech, AT&S, Brewer Science, Evatec, Hitachi Chemical, Fujifilm, Meltex, Merck, Mitsui Chemicals, Nanium, Semsysco, Süss MicroTec, Shin-Etsu and Unimicron. What follows are excerpts of that conversation.

SE: In R&D, the industry has been developing a next-generation fan-out technology using a panel-level format. In panel-level fan-out packaging, you can put more die on a panel as compared to a traditional round wafer. In theory, panel-level packaging could potentially lower the cost of fan-out. What prompted Fraunhofer to begin looking at panel-level packaging?

Fig. 1: Comparison of number of die exposed on 300mm wafer to number of die on panel. Source: STATS ChipPAC, Rudolph

Töpper: Roughly 10 years ago, we started activities in embedding chips into printed-circuit boards. In the beginning people did not see any advantages with that approach. But now it seems that the substrate increasingly is becoming the biggest problem in packaging because everybody needs low-cost, high-density substrates. And so we were one of the only institutes here doing printed-circuit board technology. In addition, we also had fan-out packaging technology. We took that further. We were the first to look for panel-level molding machines. We were the first in the world to have panel-level molding. We were also working with a lot of materials and equipment suppliers. We’ve seen that you need to bring everybody to one table to have the possibility to work on this new panel-level packaging approach, because up to now it’s not clear what is the right panel size, technology, process steps, materials and applications. So it was then the time to start a consortium. Now we have companies from Asia, the U.S. and Europe.

Braun: Besides all of the panel experience from the printed-circuit board side, we also have a lot of experience on wafer-level thin-film technology, as well as assembly and molding. That is what we can bring here from the materials side to large-area processing on the equipment side like lithography.

SE: So in many respects, panel-level packaging combines some of the aspects of PCB technology and traditional wafer-level fan-out, right?

Töpper: Everybody needs high-density substrates. For sure, everyone wants to go for organic substrates. If you have 2µm line and space on organic, it’s no longer a printed-circuit board. It’s something else. We denote it as panel-level packaging, which also includes embedding components inside the substrate. When people are discussing 2µm line and space, that’s also RDL technology on a wafer. So these two worlds are coming together.

Braun: For us, it’s not single-chip packaging. It’s really heterogeneous integration. On one hand, of course, it’s what we have been doing for substrate embedding. For this, there is power electronics, which is one of the main drivers here. Then, on the other hand, for fan-out we see a lot of RF packaging at the moment. We also have heterogeneous integration and a lot of antenna integration. This means you need area space. That makes the panel more attractive compared to a small round wafer.

SE: What’s the problem in terms of doing fan-out on a traditional round wafer format?

Braun: It’s small compared to panel. If you try to put rectangular things on a round shape, you lose a lot of area. The larger the rectangular parts you use, the more area you lose on round wafers.

SE: The purpose of panel-level fan-out is to lower the cost of fan-out, right?

Braun: It’s to lower the cost. But if you say it another way, it’s also a way to scale up wafer-level technologies. In panel-level packaging, you also take the best of different worlds. So you are not only scaling up wafer technologies, but also you take from other technologies like printed-circuit boards. For this, there is a strong development in new materials, but also in new lithography tools such as laser direct imaging. This comes more from the printed-circuit board industry than the semiconductor industry, for example.

SE: Let’s talk about the Panel Level Packaging Consortium at Fraunhofer. Are you doing fan-out or general panel-level packaging?

Braun: It’s a fan-out chip-first approach. It’s really having an assembly face down on carrier process, with over molding, debonding and RDL. In my opinion, chip-first has the biggest advantage concerning system integration and RF performance. You can combine different components without special bumping or preparation. And you can add passive components without any restrictions.

Fig. 2: Chip first vs. chip last. Source: TechSearch International

SE: What panel sizes are you working on?

Braun: Our format is 18- x 24-inch. For the first year, we are working on the half format, which is 18- x 12-inch. We have already demonstrated on 18- x 24-inch.

Töpper: For cost savings, we are sometimes working on a half format. We can process more materials on this format. But in general, we can do it on 18- x 24-inch.

SE: Have you demonstrated capabilities at both 18- x 12-inch and 18- x 24-inch?

Töpper: Yes, both.

SE: Fraunhofer is not selling panel-level packages in the commercial market, right?

Töpper: We have no production. What we do is transfer the technology. We already have transferred technology worldwide. We sometimes install a whole line in a company and start, more or less, the production together. We are non-profit and we are not a production site here. But our equipment is possible for production. Sometimes we do prototyping with a couple of thousand samples. But then, if it’s going into full production, we look for partners and transfer the technology.

SE: Within your group, Fraunhofer is also developing traditional wafer-level fan-out, right?

Braun: We have two major technology lines. One is on the wafer level and one is on the substrate level. What we bring here are competencies from both worlds.

Töpper: It is the same organization, but another group within the organization. So we have a full 300mm through-silicon wafer line. It’s fully automated.

Braun: We are also discussing downscaling from panel to wafer. You can have a cost-effective material for panel-level, which might also be down scaled or transferred to the wafer level.

SE: Let’s move back to the consortium. Fraunhofer has developed a process flow for panel-level fan-out, right?

Braun: We call it a reference process flow ready for industrialization, but it’s pre-competitive. We have partners from the equipment and materials industry. We also have at least one end-user with Intel. We also have OSATs and manufacturing partners like Nanium, AT&S and Unimicron. We have different views in the manufacturing flow. One of the other goals is to bring the partners together. You can’t do assembly without caring about lithography later and the other way around. Even if you start working on fan-out, you simply can’t take the silicon wafer out of the box and evaluate your dielectric materials. That’s doesn’t work anymore. So you have to bring the people together from different industries.

Fig. 3: Fraunhofer’s panel-level line. Source: Fraunhofer

SE: The initial goal of the consortium is to develop panel-level fan-out 10µm line and space with two layers. Then, the next step is to develop 5-5µm, right?

Braun: For the first year, we have fixed targets. We already have a test vehicle looking a bit like a processor/memory package. For the second year, there is more of a proposal. We are now discussing that with our partners. We will look beyond 10µm line and space. But people don’t often talk about pad sizes and pad pitches, because it is even more challenging when looking at the entire process flow.

SE: Have you demonstrated 10-10µm with panel-level fan-out?

Braun: Yes.

SE: There are several challenges in panel-level fan-out packaging. For one thing, several consortiums and OSATs are working on different panel sizes. Do we need a standard panel size in the industry?

Töpper: From the equipment vendors we get a strong message that we need a standard. They don’t want to develop a different machine for each size. Then, they need handling concepts and transportation systems. If people are talking about 2µm line and space, you need a very good concept in handling and storage. Otherwise, you could have big yield issues.

SE: Do you see the industry settling on a panel standard?

Töpper: If you get to very high density, people will go for 2µm line and space. That will be one size. But there might be different sizes, perhaps on 10µm line and space, because you have more possibilities on the equipment. It’s something we are discussing in the consortium.

SE: What are the big challenges in panel-level fan-out?

Braun: Technology-wise, we have a lot of new materials and equipment. There must be development on the materials and equipment. And, of course, there are questions about warpage. In handling, it is also challenging, because everything is different. It’s different than printed-circuit boards and flat panels. Molded panels are very brittle. It’s easy to break. There are new concepts needed for handling.

Töpper: In the wafer, there are spin-on materials, which are not that easy on the panel. We are looking at new dry films and low-k dielectrics.

SE: What particular tool or process is the most challenging?

Töpper: I would say it’s a combination of all of them. In assembly, for example, you can use different molding compounds. Different molding compounds have an effect on the warpage, stiffness and the shape of the panels. You have so many different combinations.

SE: What type of lithography technology are you using for panel-level fan-out? What are the challenges?

Töpper: We have different equipment. On the wafer, we are using mask aligners. For the panel, we have laser direct imaging. Now, we are talking with our partners about other possibilities.

Braun: Even laser ablation.

Töpper: We have already talked a lot about 2µm line and space, but nobody is discussing the via sizes in the dielectrics. In some of the dielectrics, it’s not that easy to develop. If you have a 10µm via on 2µm lines, they don’t fit with each other. You need smaller vias. Otherwise, you have issues with dielectrics.

SE: Is it difficult to scale panel-level fan-out beyond 5-5µm?

Töpper: There are companies that have shown SEM pictures on 2µm line and space. But up to now, nobody has talked about the yield on that. So we also want to look at where is the yield here.

SE: What about pick-and-place in the assembly part of the flow?

Braun: Pick-and-place is a bottleneck. That is on the wafer. It’s the same on the panel level. In pick-and-place, the die is the same. It’s independent if you place it on a wafer or a panel. Typically, the higher the accuracy of the assembly, the slower the machine. The equipment suppliers are working on that. We will also see new machines coming up next year on panel-level with higher accuracy and higher speed. But generally, that is a bottleneck. Honestly, I don’t see many alternatives coming up.

SE: What about molding tools?

Braun: There are at least three suppliers with panel equipment available.

SE: What about fine-pitch inspection?

Braun: It’s available, but it depends on what you want to see. If you want simple inspection, and want analysis in particle residues and shortened lines, that is available. Let’s say if you want to combine it with a measuring tool. Maybe you need it for a feedback loop for how accurate is your assembly and die shifting. That is a combination that is more challenging.

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