Interconnect Challenges Grow

It’s becoming apparent that traditional chip scaling is slowing down. The 16nm/14nm logic node took longer than expected to unfold. And the 10nm node and beyond could suffer the same fate.

So what’s the main cause? It’s hard to pinpoint the problem, although many blame the issues on lithography. But what could eventually hold up the scaling train, and undo Moore’s Law, is arguably the most problematic part of device scaling—the backend-of-the-line (BEOL).

The BEOL is where the interconnects are formed within a device. Interconnects are tiny wiring schemes in devices and they are becoming more compact at each node, causing an unwanted resistance-capacitance (RC) delay in chips.

In fact, the interconnects are lagging behind the transistor portion of the device. The transistor is fabricated in the so-called front-end-of-the-line (FEOL).

“The scaling roadblocks that the interconnect faces need to be addressed,” said Sree Kesapragada, global product manager at Applied Materials. “A good analogy is that you have a Ferrari, which is the finFET transistor. But you are stuck in traffic because your interconnect is not keeping up with the Ferrari.”

And the problems are escalating at each node. For example, the Georgia Institute of Technology calculated the average delay in a chip based on several hypothetical scenarios. In a chip, the average delay due to copper resistivity increased by 7.6% from 45nm to 22nm, according Georgia Tech. But on average, the delay jumped by 21.8% from 22nm to 11nm and by 48% from 11nm to 7nm, according to researchers.

“Going from 45nm to 20nm, the delay actually scales quite well,” said Azad Naeemi, assistant professor at Georgia Tech. “But once you get to 11nm, you can’t improve the performance, even if your devices are getting better because of the interconnects. Your circuit delay goes up unless you can somehow improve the interconnects.”

To help the industry get back on track, Imec and its partners recently rolled out a new logic roadmap. As part of the roadmap, the R&D organization outlined a new interconnect path down to 7nm.

Based on Imec’s roadmap, the industry hopes to migrate to new and complex materials, such as cobalt, manganese and perhaps ruthenium, for the metallization schemes. And in the distant future, the industry is exploring carbon nanotubes and graphene.

All told, the industry will require new BEOL breakthroughs on several fronts, such as tools, materials and process schemes.

In addition, to circumvent the RC delay issues, chipmakers continue to pursue a separate path. Instead of scaling, the idea is to go vertical. On this front, there are several options, such as advanced stacked die, monolithic 3D and vertical nanowires.

The problems
In a device, there are two types of BEOL interconnect wires, intermediate and global. Intermediate wires provide the lower-level connections in a device. The global wires connect the intermediate layers.

Adding to the complexity is that chipmakers have inserted another wiring hierarchy starting at 20nm. The scheme, dubbed the middle-of-the-line (MOL), involves the local interconnects in a device.

“The big part of the performance of a circuit is determined by interconnects,” Georgia Tech’s Naeemi said. “Transistors account for less than 50% of the delay. The rest is coming from resistance and capacitance within the cell, between the cell and in the interconnect.”

At each node, the interconnect becomes more complex. For example, Apple’s A7 processor, which first appeared in the iPhone 5S, is a 64-bit system-on-a-chip (SoC) based on a 28nm process.

The A7 is a 10-level metal device. It also consists of more than 1 billion transistors and more than 10 billion vias, according to analysts. And if the total length of the copper wires was measured in the A7, it would amount to an astounding 20 kilometers, they added.

On top of that, the interconnect wires are only a few atoms thick. The distance between the wires is only a few atoms wide. And what’s more, the wires must be perfectly aligned on top of each other. “Since you are making these connections one level at a time, you have to make sure the connections land exactly on a pre-made metal line,” Applied’s Kesapragada said. “Any one via that hasn’t landed is going to reduce your chip yield by like 20%.”

The problems get worse starting at 16nm/14nm. The capacitance per unit length remains constant, but the resistance per unit length increases. “The resistance is increasing because of grain boundary scattering, surface scattering and barrier thickness,” Georgia Tech’s Naeemi said.

Any solutions?
In the BEOL, there are many process steps, which fall into two categories—patterning and the dual damascene flow. Initially, in the flow, each level of a given chip structure must be patterned to create the wiring schemes.

Today, chipmakers use 193nm immersion and multiple patterning in the BEOL. At 7nm, chipmakers would prefer to use extreme ultraviolet (EUV) lithography for BEOL patterning, at least for the more critical layers.

EUV could reduce the process steps, thereby lowering cost. But if EUV misses the window at 7nm, chipmakers would extend optical, which is an expensive solution at best.

Meanwhile, after a given level is patterned, the device goes through the copper dual damascene process. This process involves three main parts—metallization, low-k dielectrics, and the capping layer.

In the metallization flow, a structure undergoes a diffusion barrier etch step. Then, a via dielectric is deposited. An etch step then forms a gap, where the lines and vias are formed.

For years, chipmakers basically used the same metallization scheme. A thin barrier layer of tantalum (Ta) and tantalum nitride (TaN) materials are deposited using physical vapor deposition (PVD). Ta is used to form the liner and TaN is for the barrier. The barrier layer is coated over by a copper seed barrier. And finally, the structure is electroplated with copper and ground flat using chemical mechanical polishing (CMP).

At 20nm, the metallization scheme began to change. TaN is still utilized for the barrier. But using chemical vapor deposition (CVD), cobalt (Co) began to replace Ta for the liner. Compared to Ta, Co provides a superior wetting layer for copper films.

At 16nm/14nm, meanwhile, chipmakers are migrating from planar transistors to finFETs. For the metallization scheme, many foundries are using TaN for barrier and Co for the liner. Some holdouts continue to extend TaN and Ta.

Then, at 10nm, chipmakers plan to extend the finFET. For the metallization scheme, the leading candidate is TaN for the barrier and Co for the liner, according to Imec’s roadmap. Ruthenium (Ru) is another option for the liner at 10nm, according to Imec.

Ru has better wetting properties than Co, but Ru is difficult to polish. “Ru, as an option, is being pushed out,” Applied’s Kesapragada said. “It’s not at 10nm. Even at 7nm, customers are back and forth. It’s still on the table as a back-up option.”

For 7nm, there are two transistor options on the table—finFETs and the lateral nanowire FET, according to Imec. For the BEOL, the leading candidate is Co for the liner and manganese (Mn) for the barrier, according to the R&D organization.

By then, chipmakers may consider using Mn-based self-forming barriers. “Self-forming barriers can improve the scattering of the different interfaces,” said Mehul Naik, a principal member of the technical staff at Applied Materials.

Also at 7nm and beyond, the industry is exploring new gap fill techniques. In the lab, for example, LAM Research and IMEC are developing a novel bottoms-up prefill technique for vias and contacts.

Using electroless deposition (ELD) of Co, the technique results in a void-free filling of vias and contact holes. “Hopefully, we don’t need a barrier,” said Larry Zhao, a technical director at Lam Research. “But if we need a barrier, we pretty much need to do a selective deposition process on the sidewall.”

At 5nm, though, there is no clear-cut BEOL solution on the table. The industry is exploring several options, many of which are somewhat exotic. For example, Georgia Tech is exploring the idea of using a hybrid material approach. Copper or tungsten could be used for the power lines within the interconnect structure, while aluminum could be utilized for the signal wires.

“We could use one material only for power distribution. And then use another material for signal distribution, where the electromigration is not as severe,” Georgia Tech’s Naeemi said. “The wiring pitch for copper wires will be several times relaxed, which lowers the cost.”

Then, of course, there are carbon nanotubes and graphene. “A lot of breakthroughs must happen for graphene,” he said. “As soon as you start to pattern graphene, then the edges may not be perfectly smooth and the electrons scatter.”

There are other options on the table. Instead of traditional scaling, one idea is to go vertical by moving towards advanced stacked die and other 2.5D/3D IC approaches.

So far, though, 2.5D/3D technology is taking longer than expected to develop due to an assortment of technical and cost challenges.

More recently, though, the technology is gaining steam. The first wave of stacked memory and 2.5D graphics chips is entering the market. “TSVs are taking off where the applications demand it and can afford it,” said Ramakanth Alapati, director of packaging strategy and marketing at GlobalFoundries.

For some applications, the benefits are clear with 2.5D/3D technology. “You essentially eliminate a lot of the long wires by going 3D,” Alapati said. “There is a systems-level performance gain you get with in-package memory.”

So when will 2.5D/3D chips take off and move into the mainstream? “It’s about two to three years away,” said Prashant Aji, senior technical director at KLA-Tencor. “People say that cost will be the driver. We feel that functionality will be the driver.”