More EUV Mask Gaps

Extreme ultraviolet (EUV) lithography is at a critical juncture.

After several delays and glitches, EUV is now targeted for 7nm and/or 5nm. But there are still a number of technologies that must come together before EUV is inserted into mass production. And if the pieces don’t fall into place, EUV could slip again.

First, the EUV source must generate more power. Second, the industry needs better EUV resists. And finally, the industry needs to solve some large and critical issues in the EUV mask infrastructure.

In fact, EUV masks could make or break the technology. At present, there are two big gaps in the EUV mask arena—actinic inspection and pellicles. Of the two, the pellicle is getting the most attention. “The biggest challenge is the pellicle,” said Uday Mitra, vice president of etch and patterning strategy at Applied Materials.

Basically, a pellicle is a thin, transparent membrane that covers a photomask during the production flow. The pellicle prevents particles and contaminants from falling on the mask. If a particle lands on a mask, the scanner would likely print an unwanted defect on a wafer.

Fig. 1: Prototype pellicle. Source: ASML

Actinic inspection, meanwhile, uses the same 13.5nm wavelength as EUV for inspection purposes. But the industry is still several years away from developing this tool type. So for now, chipmakers will use existing optical inspection tools for EUV masks.

There are other issues in the EUV mask infrastructure. Defect-free mask blanks and faster write times are the most obvious ones. The lesser known issues are 3D mask and out-of-band light effects.

And in a related issue, the industry is now developing a technology called high numerical aperture (NA) EUV. High NA impacts the mask and EUV as a whole.

The industry will need to get a handle on the EUV mask issues in order to have more realistic expectations about EUV lithography in general. To help the industry get ahead of the curve, Semiconductor Engineering has assembled a list of some of the more challenging process steps in the EUV mask flow.

Why EUV?
For years, chipmakers have been begging for EUV. Today, they are extending 193nm immersion lithography and multiple patterning from 16nm/14nm to 10nm and 7nm. This, in turn, increases the overall mask count, thereby impacting cost.

EUV promises to simplify the patterning flow, thereby reducing the mask count and cost. Unlike today’s optical lithography, which uses light to print tiny features, EUV utilizes a power source that converts plasma into light at 13.5nm wavelengths. Then, the light bounces off several mirrors before hitting the wafer.

With optical lithography tools, there are 6 lithography steps and 7 overlay metrology steps at the 28nm planar node. In comparison, with immersion/multi-patterning, there are 34 lithography steps and 60 overlay metrology steps at 7nm, according to ASML.

With EUV, there are just 9 lithography steps and 12 metrology steps at 7nm, thereby making this an ideal solution for the industry, according to ASML.

The problem is the technology is still not in production amid a number of issues. “EUV lithography has been studied for more than 20 years,” said Kurt Huang, senior director of corporate marketing at UMC. “However, it is not yet mature for mass production,”

“Currently, there is no fab using EUV lithography for volume production, only for R&D purposes,” Huang said. “To date, one of the key issues of EUV lithography is its slow throughput. Furthermore, there are issues such as blanks, mask inspection and repair.”

EUV has made progress, however. “The state of EUV technology is much better than a year ago or two years ago,” said , chief executive of D2S. “The question is whether ‘much better’ is good enough for production. Specifically, people talk about the power source. The other question is the uptime. The question is how long is it going to take to get to the point where EUV is reliable enough that it’s not down half the time.”

For now, chipmakers are targeting EUV for 7nm and/or 5nm. In fact, Intel and Samsung are targeting EUV for 7nm. In contrast, GlobalFoundries and TSMC will extend immersion/multi-patterning to 7nm and hope to insert EUV at 5nm.

Mask blanks
Meanwhile, there are other challenges as well, particularly in the EUV mask flow. The photomask itself is a critical part of the IC supply chain. A chipmaker designs an IC, which is then translated into a file format. Then, a photomask is developed based on that format.

Basically, the photomask is a master template for a given IC design. After a mask is developed, it is shipped to the fab. The mask is placed in a lithography scanner. The scanner projects light through the mask, which patterns the images on a wafer.

The photomask fabrication process starts with a mask blank, which is the base substrate of a photomask. Basically, an optical mask blank consists of an opaque layer of chrome on a glass substrate.

In contrast, an EUV mask blank consists of 40 to 50 alternating layers of silicon and molybdenum on a substrate. A number of absorbers are situated on this stack.

The EUV blank serves as a mirror or reflector for EUV light. And in theory, the EUV mask blank must be defect free.

In the EUV mask blank production process, however, the substrates are inadvertently riddled with unwanted defects, such as pits and bumps. Over time, vendors have reduced the number of phase defects on EUV mask blanks to single digit numbers.

Still, mask makers must find a way to prevent those unwanted defects from showing up on the photomask. Otherwise, the defect may get printed on the wafer.

To solve the problem, mask makers must locate the defect. Then, the defect is marked and covered by the absorber. In the flow, the e-beam patterns the mask, but it avoids the defect using pattern shifting techniques.

This technique works, but it’s complex and time consuming. “With EUV lithography, we need a lot more work to bring the infrastructure to maturity, particularly low-defect mask blanks,” said Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries.

Writing the mask
Following this process, a mask blank is then sent to the photomask shop. Then, the next step in the flow is to pattern the mask blank using e-beam tools. Using today’s single-beam e-beam tools for optical masks, the average mask write time ranges from 8 to 15 hours per mask set, according to experts.

EUV masks are far more complex, however. For EUV, the sub-resolution assist feature (SRAF) sizes on the mask could range anywhere from 32nm to 40nm, compared to 60nm or so for optical. Or for EUV, the SRAF 1x design sizes could range anywhere from 8nm to 10nm, compared to 15nm for optical, according to Mentor Graphics.

With single-beam e-beam tools, EUV mask write times could jump anywhere from a whopping 50 to 100 hours per mask set, according to experts, who said those figures are simply unacceptable for customers.

There is a solution, however. Seeking to reduce the write times in masks, IMS Nanofabrication recently introduced the world’s first commercial multi-beam mask writer. Equipped with 262,144 beams, the system promises to speed up mask production. It can write a complex mask in just 10 hours.

NuFlare is also developing a multi-beam mask writer. “Multi-beam would help chipmakers even more by enabling more complex mask shapes that can be manufactured reliably,” D2S’ Fujimura said. “That’s a big part of the need for multi-beam. That enables better manufacturability and an increased process margin for the wafer.”

More mask issues
Other issues are cropping up for EUV masks. For some time, EUV masks have suffered from so-called 3D mask effects. In EUV, the projection optics are situated in such a way that the light hits the wafer at an angle of some six degrees.

On the mask, though, there is an absorber that juts out on the top. The absorber defines the dark areas on the mask. The absorber, however, interferes with the light hitting the mask, causing shadowing effects, sometimes called 3D mask effects.

This complicates the OPC process and causes overlay errors, according to Imec in a recent paper in the BACUS newsletter. Imec, GlobalFoundries/SUNY Poly and Toshiba/DNP are separately addressing the problem with a similar idea.

As stated above, an EUV mask blank consists of 40 to 50 alternating layers of silicon and molybdenum on a substrate. Instead of those materials, researchers are exploring the idea of mask blanks with alternating layers of ruthenium (Ru) and silicon.

This, in turn, “will lead to smaller mask 3D effects,” according to GlobalFoundries and SUNY Poly in a separate paper in the BACUS newsletter.

EUV masks based on Ru and silicon are still in R&D. In a more immediate issue, EUV masks also suffer from out-of-band light effects. When the EUV light hits the mask, it contains various wavelengths that are not required. This is known as out-of-band light, which impacts the EUV mask.

To solve the problem, Toppan and others are developing a so-called light-shielding black border technology. The black border involves a specialized three-dimensional structure, which is located on the periphery of an EUV mask. Toppan’s technology reduces the reflection of out-of-band light by 70%.

Mask inspection
Meanwhile, after mask writing step, the EUV mask undergoes a rigorous metrology and inspection flow. There are several possible ways to inspect EUV masks—actinic; e-beam; and optical.

Today, traditional optical-based inspection tools are being used to find defects for both optical and EUV masks. 193nm-based optical inspection works for current EUV masks, but optical may run out of steam in terms of resolution in the future. Meanwhile, e-beam inspection can also work, but it’s slow in terms of throughput.

The industry wants actinic inspection, which can supposedly find more defects than optical in EUV masks. There is a problem, though. No such tool exists today.

Looking to help address the issue, KLA-Tencor recently introduced two 193nm wavelength optical mask inspection systems. The system can handle both optical and EUV masks.

“There are different challenges between them,” said Mark Wylie, product marketing director at KLA-Tencor. “The platform is set up so that we can use transmitted and reflective light. For EUV, we have to use our reflective light channel. And then we have to use similar techniques that we use in our wafer inspection tools, with off-axis and optimized illumination conditions, to extract the defects.”

Pellicle problems
Perhaps the biggest issue is EUV pellicles. Used in all optical masks, a pellicle is a thin-film membrane that sits on the reticle. It prevents particles and contaminates from falling on the mask.

The EUV pellicle provides a similar function, but it’s based on a different technology. ASML, the sole supplier of EUV pellicles in the industry right now, is developing a polysilicon-based EUV pellicle that is only 50nm thick.

In operation, EUV pellicles must withstand an enormous amount of heat. When EUV light hits the pellicle, the temperature of the membrane will heat up anywhere from 600 to 1,000 degrees Celsius.

In theory, the pellicle will dissipate the heat. But at those temperatures, there are also fears that the EUV pellicle could deteriorate during processing, causing damage to the EUV mask and scanner.

“Having a pellicle that can withstand the power required is tough,” Applied’s Mitra said. “The question for the pellicle is the absorption. How much of the light goes through is the problem.”

Even when the pellicles are developed and shipped, there are various issues. Mask makers can’t use existing 193nm mask inspection tools, or e-beam systems, to directly inspect EUV masks with a polysilicon-based pellicle. This material is opaque at the deep ultraviolet range.

ASML has solved part of the problem—it has devised a retractable pellicle. In the flow, the EUV mask is manufactured and the pellicle is placed on top. In the inspection process, the EUV pellicle is automatically raised and removed from the mask. Then, once the inspection process is finished, the pellicle is automatically lowered and re-attached to the EUV mask.

A retractable pellicle is a complex mechanism. To enable this process, the EUV mask itself requires a small post or stake. The post is set upright and glued to the mask.

It supports the retractable pellicle when it opens and closes. So far, though, the industry hasn’t decided where to exactly place the post on the mask. There are three options for the location of the posts:

• The post is glued to the absorber. This simplifies the process, but it is prone to defects, according to Guojing Zhang, manager of Advanced Mask Technology of Components Research at Intel, in a recent presentation.
• The post is glued to the multi-layer stack. This, however, could cause peeling on the mask, Zhang said.
• It is glued to the mask surface. This is the best option. “Those risks can be avoided,” he said.

What’s next?
ASML recently took a 24.9% minority stake in Carl Zeiss SMT, a subsidiary of Zeiss, for 1 billion euros. For years, Carl Zeiss has developed the projection optics for ASML’s EUV scanners.

As part of the new plan, the companies will work on the next generation of EUV optics based on high NA technology. The current EUV systems have an optical system with an NA of 0.33. The new optics will have an NA larger than 0.5, enabling EUV to scale beyond the 5nm node.

For high NA, ASML and Zeiss are co-developing an anamorphic lens for EUV. By definition, an anamorphic lens produces unequal magnifications along two axes perpendicular to each other. In EUV, the two-axes lens would support 8X magnification in the scan mode and 4X in the other direction. An anamorphic lens promises to enable higher resolutions.

But the EUV scanner could take a throughput hit. It would expose the wafer at only half the field size, as opposed to full field sizes with today’s EUV scanners. Then, a mask maker would have to cut the field into two or four masks and then stitch them together. Stitching, according to mask makers, is a long and painful process. “That’s very challenging in terms of overlay and throughput,” according to one mask maker.

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