Next-Gen Mask Writer Race Begins

By Mark LaPedus - 19 Oct, 2017 - Comments: 5

Competition is heating up in the mask writer equipment business as two vendors—Intel/IMS and NuFlare—vie for position in the new and emerging multi-beam tool segment. Last year, Intel surprised the industry by acquiring IMS Nanofabrication, a multi-beam e-beam mask writer equipment vendor. Also last year, IMS, now part of Intel, began shipping the world’s first multi-beam mask writer f... » read more

More EUV Mask Gaps

By Mark LaPedus - 17 Nov, 2016 - Comments: 12

Extreme ultraviolet (EUV) lithography is at a critical juncture. After several delays and glitches, [gettech id="31045" comment="EUV"] is now targeted for 7nm and/or 5nm. But there are still a number of technologies that must come together before EUV is inserted into mass production. And if the pieces don’t fall into place, EUV could slip again. First, the EUV source must generate more ... » read more

7nm Fab Challenges

By Mark LaPedus - 21 Apr, 2016 - Comments: 3

Leading-edge foundry vendors have made the challenging transition from traditional planar processes into the finFET transistor era. The first [getkc id="185" kc_name="finFETs"] were based on the 22nm node, and now the industry is ramping up 16nm/14nm technologies. Going forward, the question is how far the finFET can be scaled. In fact, 10nm finFETs from Samsung are expected to ramp by ye... » read more

Impact Of Illumination On Model-Based SRAF Placement For Contact Patterning

By Various Writers - 19 Feb, 2014 - Comments: 1

Sub-Resolution Assist Features (SRAFs) have been used extensively to improve the process latitude for isolated and semi-isolated features in conjunction with off-axis illumination. These SRAFs have typically been inserted based upon rules which assign a global SRAF size and proximity to target shapes. Additional rules govern the relationship of assist features to one another, and for random log... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: SRAF

Next-Gen Mask Writer Race Begins

More EUV Mask Gaps

7nm Fab Challenges

Impact Of Illumination On Model-Based SRAF Placement For Contact Patterning