More Lithography/Mask Challenges (Part 3)

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at Imec; Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries; Regina Freed, managing director of patterning technology at Applied Materials; Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To view part one of this discussion, click here. Part 2 is here.

SE: Moore’s Law is still relevant, but the cadence of the leading-edge process nodes is slowing down. Each node is becoming more challenging. Yet, there is still a huge demand for chips and we still need more compute power, right?

Fujimura: Absolutely. As a consumer of computing power, which is what we do, there is no end in sight. We need a lot more. If we had 10 times as much for the same cost today, we would use it to improve various applications in semiconductor manufacturing. There is a lot more that can be done. In autonomous driving, for example, it’s not so much in actually driving the car, but it’s in training the system. It requires a lot of computing. Then, particularly with GPU acceleration, we will continue to experience Moore’s Law scaling in both fine-grain and coarse-grain parallelism with the single instruction, multiple data programming paradigm. Even with CPU-based computing, where clock speed is no longer scaling, coarse-grain parallelism continues to scale. We continue to be able to do more in the same amount of time and at the same cost than the previous generation. And certainly, those of us in software for semiconductor manufacturing definitely need more computing power. A lot more. Like I said, if we had 10 times as much for the same cost today, we would love that. It’s fair to say that all other scientific and engineering computing communities are in a similar situation. We all would love more, and can monetize more computing faster. The explosion in demand from deep learning training for all computing worlds, not just scientific or engineering, will provide for an acceleration in that demand. Ten years ago, I heard people say, ‘We already have plenty of compute power. We don’t know how to use more computing power.’ This is mostly referring to IoT devices, smart phones and laptops. I don’t hear that any more.

McIntyre: The applications driving the market are all over the place. The automotive sector, the health care sector, the energy sector, and others are incorporating more silicon and in more domains. Regardless of what the technique ends up being, there is a growing demand or hunger for technology from the consumer. As you make better hardware, you make better software. That needs better hardware. It’s just keeps this cycle going.

Freed: You see a lot of diversification coming. You might have various technologies in your car. That might be different than what’s in the cloud. In the cloud, you might have different kinds of architectures. Then, in the foundry, there are different types of devices being designed. Some of them are low power. Some of them are high performance.

Levinson: There is a lot of opportunity in software. Companies continue to produce better and better processors. They get more and more memory. But the laptop performance gets worse. That’s a problem. We create better hardware. The software reduces the performance in the end, so the consumer is not going to buy a lot of it. We have a serious problem on the software side.

SE: It appears that today’s finFET transistors will extend to the 5nm foundry node. What types of transistor types or architectures may appear beyond 5nm? And then, how do we get there in terms of patterning? What types of lithography techniques are required at those nodes?

Fujimura: I have trust that this need for more computing is going to be met by the community somehow. It might be a lot more expensive. But I think it’s going to continue. Then, people are talking about something called neuromorphic computing. It’s basically computing in memory. Nanoimprint and DSA can be applied here. There is also increased software availability in deep learning. And everybody doing that is going to make it easier to program it.

McIntyre: From a device side, our finFET-based devices will likely evolve into a nanowire-based world. This opens up the possibility to do other things. Instead of having a separate nFET and pFET in the device, you can put one on top of each other in stacked nanowires. That’s called a complementary FET or CFET. You can also take the channel and orient it vertically. In addition, you start using magnetic RAM-like devices in the backend for some of your cache memories. The main point is that you will have a bunch of different options. You will probably see that you can start using one option for the main processor. Another option can be used in the graphics piece. Then, another option might be used for the SRAM. So you end up in this next phase, which is referred to as system technology co-optimization. You take all of these pieces and integrate them. You can stack them on top of each other. Meanwhile, in addition to what we are doing in patterning, you can optimize the whole system. It will be coupled with High-NA EUV or aggressive pitch generation techniques for quite some time.

Fig. 1: Next-gen transistor architectures. Source: Imec

Hayashi: With the difficulties in scaling, people will discover very different architectures for data processing. A new architecture may not need aggressive scaling. It may be a combination of functional devices. They might be stacked in a 3D-like fashion.

Levinson: It’s hard to predict what the device physicists will come up with. It’s too far out. But one of them might be nanosheets. What’s interesting about that from a patterning point of view is that we go back to having devices with variable widths. So today, our fins are one width. We can make them with spacer techniques and so forth. If we go back to variable widths, as what we did in the days of planar transistors, it’s highly desirable to print those directly with EUV lithography. That puts a lot of stress on the line-edge roughness. There will be a need for much less LER. This will be interesting to see how this plays out. If you go back to the old ITRS roadmap, the industry said the feature that was most sensitive to linewidth variation was the gate of microprocessors. And so, the LER specifications in the old ITRS were derived based on the requirements of planar transistors from microprocessors. Those specifications then became invalid when we went to finFETs. But now, if we go back to devices with similar patterning requirements as the old planar transistors, we are back on very aggressive line-edge roughness.

Fig. 2: Cross-section simulation of (a) finFET, (b) nanowire, and (c) nanosheet. Source: IBM

Freed: We will probably see a lot of different things. Each new option comes with a new set of problems. A lot of them come with very tight control specs. I do know that we will add a lot more materials. They are going be different from the ones we are using in the periodic table today. And then we may move from optics to materials science, because optics are becoming more difficult. There is a lot more to be done with materials. We are going more toward 3D, and that’s one of the places where we can do certain things.

SE: As we have seen, the current technologies last longer than expected. Optical lithography is a good example, as the technology continues to be the workhorse tool in the fab. The same is true with the nodes. The mature technologies are still viable. And on the leading-edge, many think 7nm will be a long-running node. How will this all play out?

Freed: Customers are still moving to the next nodes relatively fast. There is a demand driver to do that. And then we see other customers staying on nodes longer because they have a different business model. That’s a mix that will continue to happen. We will see both. You see some nodes remaining popular because they make sense for a subset of end customers. Then, you’ll see a subset of end customers driving to move to smaller nodes because it makes sense for them.

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