RISC-V Challenges And Opportunities

Semiconductor Engineering sat down to discuss open instruction set hardware and the future of RISC-V with Ben Levine, senior director of product management in Rambus’ Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation.

(L-R) Ben Levine, Jerry Ardizzone, Megan Wachs, Rishiyur Nikhil.

SE: How do you make money off an open ISA?

Nikhil: We do systems around RISC-V cores to help bring those cores to market. There are lots of open source cores out there and they get a lot of attention, but between getting a core and actually fitting it out in a system — comparing multiple different cores and figuring out which one might be best for you, measuring them in some scientific way — all of that requires certain kinds of infrastructure around it. Our company focuses on that kind of work, building products that will help you evaluate RISC cores, have a platform where you can modify RISC cores and have a complete system running around it, et cetera. It’s not making money on the core itself. It is on the things around it.

SE: So the picks and shovels for the miners?

Nikhil: The picks and shovels and the jeans.

Wachs: We are really enabling extreme customization and faster time to market, and that is one thing RISC-V enables because of its extremely customizable ISA. We can build an extremely customizable SoC around that.

Ardizzone: We’re a pure-play processor IP company, and to make money in this business we can’t do it on our own. We need RISC-V to be successful. It needs to be widely adopted, and we need a large third-party ecosystem that is robust. So in semiconductor IP, the single largest market segment for IP is processor IP. We are in that business, and our job is to go out and get some market share, and we are not going to do that unless RISC-V is successful. There’s plenty of market out there, so we just need to provide great products that differentiate and provide value to our customers.

Levine: We are actually involved in the RISC-V ecosystem in a couple of different ways. One is we produce security IP. Our bread-and-butter business is selling security IP — programmable roots of trust to companies making chips. And our latest generation uses a RISC-V processor that we developed specifically for security. RISC-V was really a game changer for us because it let us control the architecture and the microarchitecture and do things that enhance the security in ways that we couldn’t if we were using third-party processor IP. The other way we are involved in RISC-V is there are security solutions out there that are tied to specific processors, and what we produce is security IP that can work with any RISC-V CPUs.

SE: Where do you see the biggest competition? Is it ARM or MIPS, or the ecosystem itself?

Wachs: I think the biggest competition is actually people wanting to do it themselves. They read the RISC-V spec, they say, ‘This is awesome and fun. I am going to do it myself.’ And then you know, they get about two thirds the way through and start realizing, ‘Oh, this is a little bit complicated.’ The biggest competition is actually internal teams.

Ardizzone: From my point of view the biggest competition for us is clearly Arm. They own about 80% of the market. So if we want to be successful and grow, we need to take some of that market share, and that’s our mission. But we also some very strong competitors out there, and as they grow, they will become our main competition.

Levine: In regard to the point about internal teams, we did develop our own RISC-V CPU and it was not easy and we only did it because we had a very compelling reason to do so, because we had security features that we needed to add at the microarchitecture level. If not for that, we would be better off just buying IP from someone else who specializes in that and already has the IP developed. So I think there is competition from internal teams but it is much more challenging than people realize when they start down that road.

Nikhil: In the short term it is probably Arm. And by short term I mean the next five years or so. In a classic disruptive scenario, what’s happening here right now is you eat from the bottom and you go for the embedded, the small device controllers, those kinds of things where Arm is dominant. That’s where the initial competition will come. But in time, there are companies like the vector guys—Esperanto, for example, which is doing very high-end processors—and Intel and Power processors.

SE: Is there a risk that the entire ecosystem becomes fragmented because there are too many players here? Is there any consistency across the board?

Nikhil: I am not too worried about that. The ISA, at least so far, has been fairly tightly controlled and managed well by the RISC-V Foundation. So yes, there are a lot of players, but the definition of what is a RISC-V processor comes from the Foundation, and there are rigorous tests that are coming by which you have to convince the Foundation that what you built is actually RISC-V before you can legally even call it a RISC-V processor. So from that point of view I am not too worried about the fragmentation on this front.

Wachs: And I am not too worried because it is so hard to build software. The only way we are going to be successful is by working together, and so by kind of going off in your own direction, you are just immediately behind everyone else who decided to work together. That’s what we’ve seen so far.

Ardizzone: I agree. The RISC-V Foundation carefully watches what is going on here. You have the base integer instructions that is carefully locked down. You’ve got the standard extension space, which is monitored closely, and there’s a very good ratification process to that. And then there’s the customizable space. So it’s up to all of us to make sure it doesn’t get too fragmented and out of control, because if it does it won’t succeed. As a supplier, as a third-party member and as a user, it’s in the best interest of all of us to make sure it doesn’t get fragmented.

Levine: And just to make it unanimous, I am not really worried about fragmentation either because going off in your own direction it means you are really giving up all the advantages of using RISC-V in the first place. So someone who goes down their own path is really going to quickly be stuck and losing out on the benefit. There’s really not much incentive to do that.

Nikhil: One thing that’s very unique about the RISC-V ISA is that it’s been designed with this kind of issue in mind. So it is extremely modular, and it’s been designed with reserve op code space, reserve mechanisms for extending to larger instruction lengths, etc. So people who do extensions are not randomly gluing on stuff. They are doing it in a certain structure and fitting it in a certain structured way. That limits fragmentation.

SE: A year ago at a RISC-V Foundation meeting, one of the concerns among the users was that the tools are not there, the compilers are not consistent and security is missing. By hanging together, will all of this be solved?

Nikhil: Yes. The fragmentation question is primarily going to be about whether you when you run the same program and whether you do the same thing. That is the point on which there was general agreement. Software will follow naturally. The fact that there’s a uniform hardware base will naturally bring together all these software efforts to be consistent with it.

Wachs: We’ve made it a top priority to partner with the industry providers, and I’ve seen a lot of different companies learning about RISC-V and then supporting it. We have partnered with Segger and Lauterbach, which are debugger tool companies, there are RISC-V Foundation members everywhere. It is a huge community, and all the software tool developers are seeing that it’s in their interest to support RISC-V.

Ardizzone: Absolutely, and if we don’t have great tools this isn’t going to be successful. So we’re thinking about tools all the time. It is not just the hardware or the implementation. It is a lot about the C compiler, for example. We’ve invested in that. We hired a lot of people that focus on building what we hope to be the best C compiler in the world for RISC-V, but we can’t do it alone. The entire industry needs to have different options available for different customers. Take LLVM, for example. Some people want to use a GNU compiler. So it is whatever you like, whatever your strategy is internally. And we need to support them all. And they need to be first-class tools. There’s a lot of momentum right now. At the RISC-V Roadshow in China we had good turnout and a lot of third-party vendors came and supported that. There was a lot of interest and a lot of questions about software performance and the robustness of tools. We’ve made a huge amount of progress as an industry in the last two years.

Levine: We are seeing a real virtuous cycle in RISC-V. As there is more adoption of the ISA, there is more interest in producing tools, and tools are getting better. As tools get better and the ecosystem expands, there’s more interest. And that loop just continues. There’s a lot of momentum and it will continue to grow.

Nikhil: If a big state-run player like China takes it on as official policy and they decide to go a different direction, that’s one way things could fragment. Fortunately, it hasn’t happened so far.

Related Stories
RISC-V Markets, Security And Growth Prospects
Experts at the Table: Why RISC-V has garnered so much attention, what still needs to be done, and where it will likely find its greatest success.
Building Security Into RISC-V Systems
Experts at the Table, part 2: Emphasis shifting to firmware, system-level architectures, and collaboration between industry, academia and government.
Open ISAs Gaining Traction
Emphasis on flexibility, time to market and heterogeneity requires more processing options.
Open Source Processors: Fact Or Fiction?
Calling an open-source processor free isn’t quite accurate.
The Challenge Of RISC-V Compliance
Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.