tag: 2.5D

More Pain In More Places
By Ed Sperling - 14 Mar, 2014 - Comments: 2

Pain is nothing new in to the semiconductor industry. In fact, the pain of getting complex designs completed on budget, and finding the bugs in those designs, has been responsible for decades of continuous growth in EDA, IP, test, packaging, and foundries. But going forward there is change afoot in every segment of the flow from architecture to design to layout to verification to manufacturi... » read more

The Final Deadline For EUV
By Ed Sperling - 27 Feb, 2014 - Comments: 5

When TSMC disclosed this week—in a public forum—that its production EUV lithography test had failed in one of the early test runs due to a power source issue, there were very different reactions. EUV, after all, is an emotional issue with billions of dollars invested and lots of jobs riding on this technology. To begin with, there has been the usual spin control. The message essentially ... » read more

Are Processors Running Out Of Steam?
By Ed Sperling - 24 Feb, 2014 - Comments: 1

Check out any smart phone these days and you’ll find some reference to the number of cores in the device. It’s not the number of cores that makes a difference, though—or even the clock speed at which they run. Performance depends on the underlying design for how they’re utilized, how often that happens, how much memory they share, how much interaction there is between the cores, and the... » read more

The Search For The Next Transistor
By Mark LaPedus - 20 Feb, 2014 - Comments: 3

In the near term, the leading-edge chip roadmap looks fairly clear. Chips based on today’s finFETs and planar fully depleted silicon-on-insulator (FDSOI) technologies are expected to scale down to the 10nm node. But then, the CMOS roadmap becomes foggy at 7nm and beyond. The industry has been exploring a number of next-generation transistor candidates, but suddenly, a few technologies are ... » read more

Tech Talk: Power, Performance And Area In 2.5D
By Ed Sperling - 12 Feb, 2014 - Comments: 2

The cost will be comparable at first, but the only way to improve power, performance AND area at the same time will be with a different architectural approach. [youtube vid=XAbE7jpjuMA] » read more

Experts At The Table: Yield And Reliability Issues With Integrating IP
By Ed Sperling - 27 Jan, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: As an industry we’ve got a pretty good grasp ... » read more

The Road Ahead for 2014: Semiconductors
By Brian Bailey - 23 Jan, 2014 - Comments: 1

Last week, Semiconductor Engineering examined the 2014 predictions from several thought leaders in the industry and published those predictions that related to general market trends. Many of those predictions require some advances in semiconductor technologies and fabrications capabilities. It is those predictions that will be examined in this part, followed next week by the predictions related... » read more

The End Is Near
By Ed Sperling - 30 Dec, 2013 - Comments: 0

Looking back is easier than looking forward, and looking narrow is easier than looking wide. In 2013, there were several fundamental changes. Change No. 1: IP is now a lucrative market. From Synopsys’ standpoint, it’s been a lucrative market for some time. But the acquisitions made by Cadence, beginning in late 2012, coupled with the push by ARM into the micro-server market and the flail... » read more

Where Is 2.5D?
By Ed Sperling - 19 Dec, 2013 - Comments: 3

After nearly five years of concentrated research, development, test chips and characterization, 2.5D remains a possibility for many companies but a reality for very few. So what’s taking so long and why hasn’t all of this hype turned into production runs instead of test chips? Semiconductor Engineering spent the past two months interviewing dozens of people on this subject, from chipmakers ... » read more

Industry Restructures Around Cost
By Ed Sperling - 19 Dec, 2013 - Comments: 1

Talk to any semiconductor executive these days about what’s next for their company and you’ll probably encounter the same perspective—cost will drive future design decisions. Dig a little further, however, and you’ll find no consistent strategy for reducing that cost. While the industry has three very viable solutions for improving the power and performance characteristics of SoCs—... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy