tag: 22nm

Study Shows FD-SOI Most Cost-Effective Approach at 22nm
By Various Writers - 02 Aug, 2011 - Comments: 0

By Adele Hars What are you doing at 22nm? The debate is raging in the press and forums alike. Now research firm IC Knowledge has issued a report showing that from a straight cost perspective, planar FD-SOI is a better choice than bulk. We’ve known for a while that sticking with bulk at the 22nm node would get pretty complicated. This study shows just how complicated bulk will be: abou... » read more

Troubles At 15nm
By Ed Sperling - 16 Dec, 2010 - Comments: 0

For the better part of the past decade the most advanced companies and the big foundries were targeting 22nm as the bogeyman of chip development. Now it appears the big problems will crop up at 15nm. That means two things. First, the problems that were expected to crop up at 22nm—leakage, electromigration, electrostatic discharge, layout and even verification—appear to have been pushed o... » read more

Beyond 22nm
By Ed Sperling - 15 Dec, 2010 - Comments: 0

Gary Patton, VP at IBM's semiconductor R&D Center, talks with System-Level Design about the challenges of developing chips all the way down to 15nm. [youtube vid=2wTj3EvRIRw]   » read more

Talking Heads
By Ed Sperling - 21 Oct, 2010 - Comments: 0

The use of more third-party IP inside SoCs coupled with problems encountered at advanced process nodes is turning up some interesting challenges—and pointing the industry in some interesting directions. It’s a well-known fact that third-party IP isn’t always used as it was intended. Even internally developed IP isn’t always used as prescribed. It’s not unusual for chip developers t... » read more

From Multicore To Many-Core
By Ed Sperling - 23 Sep, 2010 - Comments: 0

By Ed Sperling Future SoCs will move from multiple cores—typically two to four in a high-power processor—to dozens of cores. But answers are only beginning to emerge as to where and how those cores will be deployed and how they will be accessed. Just as Moore’s Law forced a move to multicore architectures inside a single processor because of leakage at higher frequencies, it will begi... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 02 Oct, 2009 - Comments: 0

Low-Power Design sat down with Leon Stok, EDA director for IBM’s System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys’ Implementaton Group; Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta. What follows are excerpts of that conversation. LPD: What will happen with ... » read more

System-Level Design Challenges
By Ed Sperling - 27 Aug, 2009 - Comments: 0

Prasad Subramaniam, vice president of design technology at eSilicon, talks with System-Level Design Editor Ed Sperling about the challenges at future process nodes. [youtube vid=HSgClJ9rQGk] » read more

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