SOT-Based MRAM Design At 7nm (Georgia Tech, Intel)


A new technical paper titled "Comprehensive device to system co-design for SOT-MRAM at the 7nm node" was published by researchers at Georgia Institute of Technology and Intel. Abstract "This work presents a comprehensive spin-orbit torque (SOT) based random access memory (MRAM) design at the 7nm technology node, spanning from device-level characteristics to system-level power performance ar... » read more

Stress-Related Local Layout Effects In FinFET Technology And Device Design Sensitivity


Abstract: "Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modul... » read more