3D ICs: No Simple Answers

By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Pallab Chatterjee Just how ready is the semiconductor industry for stacked die? That was the subject of a recent panel discussion involving ARM, Atrenta, Xilinx, Samsung and Mentor Graphics. The reasoning behind 3D stacking is becoming clearer at each node. I/O count and delay times are forcing different configurations, but the time frames for these changes and the gating constraints are... » read more

Power Panel: IP And Other Key Issues For Future Development

By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering chaired a DesignCon panel of low-power experts with Bhanu Kapoor, president of Mimasic; Kesava Talupuru, DV engineer at MIPS; Prapanna Tiwari, CAE manager at Synopsys, and Rob Aitken, an ARM Fellow. What follows are excerpts of their presentations and the panel discussion that followed. Prapanna Tiwari: UPF and CPF are text files that capture the power i... » read more

The Growing Importance Of Subsystems

By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Ed Sperling A growing reliance on third-party IP is beginning to expand well beyond just IP blocks and into full subsystems, opening significant growth opportunities for companies competing in this market as well as enormous business and technical challenges. The IP market is ripe for this kind of convergence. Complexity at advanced process nodes coupled with time-to-market demands has e... » read more

The Enterprise Effect

By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Pallab Chatterjee In the enterprise it’s all about speed and power—as in more speed and less power—and those changes are forcing shifts in the chip architectures as well as the processes used to develop those chips. At the Linley Data Center Conference the next generation of network control chips were discussed. The keys for the new networks are 10G data lanes to be used with 10G/4... » read more

The Missing Pieces In Power Modeling—And Who’s Going To Provide Them

By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Ed Sperling The push to develop power models is growing at each node, and at 22nm it will be virtually impossible to proceed without one or more models for power. Providing these kind of models is easier said than done, however. Creating an accurate power model requires accurate data from all the other pieces on a chip that potentially can affect the power. That includes how third-party ... » read more

Connecting System-Level Flows To Implementation Tools