tag: chiplets

Multi-Die Assemblies Require More Detailed Test Plan Earlier
By Ann Mutschler - 29 Jan, 2026 - Comments: 0

Key Takeaways Design for test takes on new urgency in complex multi-die assemblies, where it can be used to minimize downstream errors and the cost of fixing them. DFT needs to be increasingly detailed due to more connections and the inability to access some components. DFT strategies need to be developed earlier and may require multiple testing approaches. Multi-die assembl... » read more

Software-Defined Systems
By Ed Sperling - 26 Jan, 2026 - Comments: 0

Using high-level software languages to define semiconductors is faster, easier, and allows for more changes long before the RTL stage. This is especially useful for chiplets and embedded accelerators, which are narrower in scope and more targeted at different workloads and specific domains. But there are some caveats for engineers working in this space. Russell Klein, program director for Sieme... » read more

Low Temperature Cu-Cu Bonding for Advanced Packaging (NYCU)
By Technical Paper Link - 18 Jan, 2026 - Comments: 0

A new technical paper titled "Thermal stability enhancement of low temperature Cu-Cu bonding using metal passivation technology for advanced electronic packaging" was published by researchers at National Yang Ming Chiao Tung University. Abstract "This work investigates the thermal stability of Cu-Cu bonding using a thin Ag passivation layer in applications targeting advanced packaging. Co... » read more

Wafer Probe Struggles To Adapt To Multi-Die Assemblies
By Gregory Haley - 13 Jan, 2026 - Comments: 1

Wafer probe, one of the key processes for ensuring reliability in semiconductor manufacturing, is becoming increasingly unreliable in multi-die assemblies and at leading-edge nodes. For much of the semiconductor industry’s history, wafer probe occupied a stable, largely uncontested role in manufacturing. It was understood as a screening step, an electrical checkpoint to identify failing de... » read more

Secure Data Sharing Becoming Critical For Chip Manufacturing
By Laura Peters - 13 Jan, 2026 - Comments: 0

Semiconductor companies increasingly need to share data to solve problems faster, boost yield, and trace the root cause of failed devices. But to make that work, companies need assurances that their data will be secure, free from data leaks that could result in the loss of valuable IP. Data sharing is becoming critical at leading device nodes, where process variability is starting to consume... » read more

3D-IC Success Stories: Faster Bandwidth, Lower Power, On-Time Tapeouts
By Reela Samuel - 08 Jan, 2026 - Comments: 0

As scaling at advanced nodes becomes increasingly constrained by cost, yield, and power density, semiconductor innovation is shifting decisively toward 3D-IC technologies, chiplets, and heterogeneous integration. Across AI infrastructure, cloud computing, automotive electronics, and high-performance systems, design teams are moving beyond monolithic SoCs to unlock new levels of performance, e... » read more

Chip Industry’s Top Videos 2025
By The SE Staff - 30 Dec, 2025 - Comments: 0

Rising complexity, new architectures, and AI's permeation of nearly everything left engineers struggling to keep up in 2025, as evidenced by this year's viewership numbers. Among the hottest topics were verification, agentic AI, DRAM/HBM, optimization of data movement, chiplets, and heterogeneous integration, but there was steady traffic growth across all sectors. Top 10 most-watched videos ... » read more

Reliability And Traceability In Advanced Packages
By Ed Sperling - 24 Dec, 2025 - Comments: 0

The move from planar SoCs to advanced packages can improve performance and provide flexibility in large designs, which are difficult to fit onto a single reticle-sized die. But ensuring the device works as expected remains a challenge. There are multiple packaging options to choose from — 2.5D, fan-out wafer-level packaging, 3D-ICs, and various types of system-in-package — and many possible... » read more

Software-Defined Hardware-Assisted Verification: Scaling To Quadrillions Of Cycles For Verification In The AI Era
By Frank Schirrmeister - 23 Dec, 2025 - Comments: 0

The semiconductor industry is at an inflection point. The convergence of advanced multi-die architectures, AI-driven workloads, and rapidly evolving interface protocols is creating unprecedented design complexity. At the same time, market pressures demand faster time-to-market and higher performance, leaving little room for error. From data center to edge developments, users have to run softwar... » read more

3D-IC Market Outlook: Technology Roadmaps, Readiness, And Design Implications
By Reela Samuel - 23 Dec, 2025 - Comments: 0

The 3D-IC market outlook is entering a decisive phase as the semiconductor industry transitions beyond the limits of traditional Moore's Law scaling. As performance, power efficiency, and system complexity outpace what planar integration can deliver economically, vertical integration and heterogeneous system design are no longer experimental; they are becoming foundational. Advanced packagin... » read more

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